RM0090: Reference manual - STMicroelectronics

USB on-the-go high-speed (OTG_HS) RM0090
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The application is expected to write the requests for the same channel when the
Request queue space is available up to the count specified in the MCNT field before
switching to another channel (if any).
● Interrupt IN transactions
The assumptions are:
– The application is attempting to receive one packet (up to 1 maximum packet size)
in every frame, starting with odd (transfer size = 1 024 bytes).
– The receive FIFO can hold at least one maximum-packet-size packet and two
status DWORDs per packet (1 031 bytes).
– Periodic request queue depth = 4.
● Normal interrupt IN operation
The sequence of operations is as follows:
a) Initialize channel 2. The application must set the ODDFRM bit in
OTG_HS_HCCHAR2.
b) Set the CHENA bit in OTG_HS_HCCHAR2 to write an IN request to the periodic
request queue. For a high-bandwidth interrupt transfer, the application must write
the OTG_HS_HCCHAR2 register MCNT (maximum number of expected packets
in the next frame times) before switching to another channel.
c) The OTG_HS host writes an IN request to the periodic request queue for each
OTG_HS_HCCHAR2 register write with the CHENA bit set.
d) The OTG_HS host attempts to send an IN token in the next (odd) frame.
e) As soon as the IN packet is received and written to the receive FIFO, the OTG_HS
host generates an RXFLVL interrupt.
f) In response to the RXFLVL interrupt, read the received packet status to determine
the number of bytes received, then read the receive FIFO accordingly. The
application must mask the RXFLVL interrupt before reading the receive FIFO, and
unmask after reading the entire packet.
g) The core generates the RXFLVL interrupt for the transfer completion status entry
in the receive FIFO. The application must read and ignore the receive packet
status when the receive packet status is not an IN data packet (PKTSTS in
GRXSTSR ≠ 0b0010).
h) The core generates an XFRC interrupt as soon as the receive packet status is
read.
i) In response to the XFRC interrupt, read the PKTCNT field in OTG_HS_HCTSIZ2.
If the PKTCNT bit in OTG_HS_HCTSIZ2 is not equal to 0, disable the channel
before re-initializing the channel for the next transfer, if any). If PKTCNT bit in
1275/1416 Doc ID 018909 Rev 3