RM0090: Reference manual - STMicroelectronics

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<strong>RM0090</strong> Cryptographic processor (CRYP) Figure 210. AES-CBC mode decryption K 0...3 (3) I is written back into IV at the same time as P is pushed into the OUT FIFO 1. K: key; C: cipher text; I: input block; O: output block; Ps: plain text before swapping (when decoding) or after swapping (when encoding); P: plain text; IV: Initialization vectors. 2. IVx=[IVxR IVxL], R=right, L=left. 3. If Key size = 128 => Key = [K3 K2]. If Key size = 192 => Key = [K3 K2 K1] If Key size = 256 => Key = [K3 K2 K1 K0]. DATATYPE AES counter mode (AES-CTR) mode 128, 192 or 256 AHB2 data write (before CRYP is enabled) IV=[IV1 IV0] (2) DATATYPE IN FIFO ciphertext C C, 128 bits swapping I, 128 bits AEA, decrypt swapping P, 128 bits OUT FIFO plaintext P The AES counter mode uses the AES block as a key stream generator. The generated keys are then XORed with the plaintext to obtain the cipher. For this reason, it makes no sense to speak of different CTR encryption/decryption, since the two operations are exactly the same. In fact, given: ● Plaintext: P[0], P[1], ..., P[n] (128 bits each) ● A key K to be used (the size does not matter) ● An initial counter block (call it ICB but it has the same functionality as the IV of CBC) The cipher is computed as follows: C[i] = enck(iv[i]) xor P[i], where: iv[0] = ICB and iv[i+1] = func(iv[i]), where func is an update function applied to the previous iv block; func is basically an increment of one of the fields composing the iv block. Given that the ICB for decryption is the same as the one for encryption, the key stream generated during decryption is the same as the one generated during encryption. Then, the ciphertext is XORed with the key stream in order to retrieve the original plaintext. The decryption operation therefore acts exactly in the same way as the encryption operation. 128 + O, 128 bits Ps, 128 bits MS19024V1 Doc ID 018909 Rev 3 556/1416
Cryptographic processor (CRYP) <strong>RM0090</strong> Figure 211 and Figure 212 illustrate AES-CTR encryption and decryption, respectively. Figure 211. AES-CTR mode encryption AHB2 data write (before CRYP is enabled) 128, 192 or 256 AEA, encrypt 1. K: key; C: cipher text; I: input Block; o: output block; Ps: plain text before swapping (when decoding) or after swapping (when encoding); Cs: cipher text after swapping (when decoding) or before swapping (when encoding); P: plain text; IV: Initialization vectors. 557/1416 Doc ID 018909 Rev 3 +1 K0...3 (I + 1) is written back into IV at same time than C is pushed in OUT FIFO DATATYPE IV0...1(L/R) DATATYPE O, 128 bits IN FIFO plaintext P swapping I, 128 bits + P, 128 bits Cs, 128 bit swapping C, 128 bits OUT FIFO ciphertext C Ps, 128 bits ai16073b
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RM0090 Reference manual STM32F40x,
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Contents RM0090 3.5.3 Erase . . . .
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Contents RM0090 6.3.1 RCC clock con
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Contents RM0090 7.4.7 GPIO port bit
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Contents RM0090 10.3.4 Falling trig
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Contents RM0090 12.4.2 Independent
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Contents RM0090 14.3.3 Repetition c
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Contents RM0090 15.4.12 TIMx auto-r
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Contents RM0090 17.4.6 TIM6&TIM7 co
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Contents RM0090 22.1 HASH introduct
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Contents RM0090 24.3.3 Tx mailboxes
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Contents RM0090 26.3.14 Hardware fl
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Contents RM0090 28.4.13 SD I/O mode
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Contents RM0090 29.7 Ethernet inter
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Contents RM0090 31.3.1 High-speed O
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Contents RM0090 33.2 Reference ARM
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List of tables RM0090 List of table
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List of tables RM0090 Table 98. Tra
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List of tables RM0090 Table 192. NO
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List of figures RM0090 Figure 49. A
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List of figures RM0090 Figure 151.
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Documentation conventions RM0090 1
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Memory and bus architecture RM0090
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Embedded Flash memory interface RM0
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CRC calculation unit RM0090 4 CRC c
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CRC calculation unit RM0090 Bits 7:
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Power control (PWR) RM0090 Figure 7
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Power control (PWR) RM0090 When the
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Power control (PWR) RM0090 mode (se
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Power control (PWR) RM0090 A PVDO f
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Power control (PWR) RM0090 5.3.3 Sl
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Power control (PWR) RM0090 If an ac
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Power control (PWR) RM0090 I/O stat
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Power control (PWR) RM0090 Safe RTC
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Power control (PWR) RM0090 Bit 4 PV
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Power control (PWR) RM0090 5.4.3 PW
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DMA controller (DMA) RM0090 9 DMA c
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DMA controller (DMA) RM0090 9.3 DMA
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DMA controller (DMA) RM0090 Figure
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DMA controller (DMA) RM0090 Table 3
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DMA controller (DMA) RM0090 In dire
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DMA controller (DMA) RM0090 Figure
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DMA controller (DMA) RM0090 memory
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DMA controller (DMA) RM0090 9.3.11
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DMA controller (DMA) RM0090 9.4 DMA
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DMA controller (DMA) RM0090 Bits 25
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DMA controller (DMA) RM0090 9.5.5 D
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DMA controller (DMA) RM0090 15 14 1
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Interrupts and events RM0090 Table
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Interrupts and events RM0090 genera
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Interrupts and events RM0090 15 14
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Hash processor (HASH) RM0090 22.4.2
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Hash processor (HASH) RM0090 Bit 3
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Hash processor (HASH) RM0090 HASH_H
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Hash processor (HASH) RM0090 Table
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Debug support (DBG) RM0090 33 Debug
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Device electronic signature RM0090
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A ADC_CCR . . . . . . . . . . . . .
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DMA_SxM1AR . . . . . . . . . . . .
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HASH_SR . . . . . . . . . . . . . .
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RNG_DR . . . . . . . . . . . . . .
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Revision history RM0090 Revision hi
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Revision history RM0090 Table 238.
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