RM0090: Reference manual - STMicroelectronics

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<strong>RM0090</strong> Cryptographic processor (CRYP) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 k1.17 b175 k1.18 b174 k1.19 b173 k1.20 b172 k1.21 b171 k1.22 b170 k1.23 b169 k1.24 b168 w w w w w w w w w w w w w w w w CRYP_K1RR (address offset: 0x2C) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 k1.33 b159 k1.34 b158 k1.35 b157 k1.36 b156 k1.37 b155 k1.38 b154 k1.39 b153 k1.40 b152 w w w w w w w w w w w w w w w w 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 k1.49 b143 k1.50 b142 k1.51 b141 k1.52 b140 k1.53 b139 k1.54 b138 k1.55 b137 k1.56 b136 w w w w w w w w w w w w w w w w CRYP_K2LR (address offset: 0x30) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 k2.1 b127 k2.2 b126 k2.3 b125 k2.4 b124 k2.5 b123 k2.6 b122 k2.7 b121 k2.8 b120 w w w w w w w w w w w w w w w w 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 k2.17 b111 k2.18 b110 k2.19 b109 k2.20 b108 k2.21 b107 k2.22 b106 k2.23 b105 k2.24 b104 w w w w w w w w w w w w w w w w CRYP_K2RR (address offset: 0x34) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 k2.33 b95 k2.34 b94 k2.35 b93 k2.36 b92 k2.37 b91 k2.38 b90 k2.39 b89 k2.40 b88 w w w w w w w w w w w w w w w w 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 k2.49 b79 k2.50 b78 k2.51 b77 k2.52 b76 k2.53 b75 k2.54 b74 k2.55 b73 k2.56 b72 w w w w w w w w w w w w w w w w CRYP_K3LR (address offset: 0x38) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 k3.1 b63 k3.2 b62 k3.3 b61 k3.4 b60 k3.5 b59 k3.6 b58 k3.7 b57 k3.8 b56 w w w w w w w w w w w w w w w w 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 k3.17 b47 k3.18 b46 k3.19 b45 k3.20 b44 k3.21 b43 k3.22 b42 k3.23 b41 k3.24 b40 w w w w w w w w w w w w w w w w k1.25 b167 k1.41 b151 k1.57 b135 k2.9 b119 k2.25 b103 k2.41 b87 k2.57 b71 k3.9 b55 k3.25 b39 k1.26 b166 k1.42 b150 k1.58 b134 k2.10 b118 k2.26 b102 k2.42 b86 k2.58 b70 k3.10 b54 k3.26 b38 k1.27 b165 k1.43 b149 k1.59 b133 k2.11 b117 k2.27 b101 k2.43 b85 k2.59 b69 k3.11 b53 k3.27 b37 k1.28 b164 k1.44 b148 k1.60 b132 k2.12 b116 k2.28 b100 k2.44 b84 k2.60 b68 k3.12 b52 k3.28 b36 k1.29 b163 k1.45 b147 k1.61 b131 k2.13 b115 k2.29 b99 k2.45 b83 k2.61 b67 k3.13 b51 k3.29 b35 k1.30 b162 k1.46 b146 k1.62 b130 k2.14 b114 k2.30 b98 k2.46 b82 k2.62 b66 k3.14 b50 k3.30 b34 k1.31 b161 k1.47 b145 k1.63 b129 k2.15 b113 k2.31 b97 k2.47 b81 k2.63 b65 k3.15 b49 k3.31 b33 k1.32 b160 k1.48 b144 k1.64 b128 k2.16 b112 k2.32 b96 k2.48 b80 k2.64 b64 k3.16 b48 k3.32 b32 Doc ID 018909 Rev 3 582/1416
Cryptographic processor (CRYP) <strong>RM0090</strong> CRYP_K3RR (address offset: 0x3C) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 k3.33 b31 k3.34 b30 k3.35 b29 k3.36 b28 k3.37 b27 k3.38 b26 k3.39 b25 Note: Write accesses to these registers are disregarded when the cryptographic processor is busy (bit BUSY = 1 in the CRYP_SR register). 20.6.11 CRYP initialization vector registers (CRYP_IV0...1(L/R)R) k3.40 b24 w w w w w w w w w w w w w w w w 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 k3.49 b15 k3.50 b14 k3.51 b13 k3.52 b12 k3.53 b11 k3.54 b10 k3.55 b9 k3.56 b8 w w w w w w w w w w w w w w w w Address offset: 0x40 to 0x4C Reset value: 0x0000 0000 The CRYP_IV0...1(L/R)R are the left-word and right-word registers for the initialization vector (64 bits for DES/TDES and 128 bits for AES) and are used in the CBC (Cipher block chaining) and Counter (CTR) modes. After each computation round of the TDES or AES Core, the CRYP_IV0...1(L/R)R registers are updated as described in Section : DES and TDES Cipher block chaining (DES/TDES-CBC) mode on page 550, Section : AES Cipher block chaining (AES-CBC) mode on page 554 and Section : AES counter mode (AES-CTR) mode on page 556. IV0 is the leftmost bit whereas IV63 (DES, TDES) or IV127 (AES) are the rightmost bits of the initialization vector. IV1(L/R)R is used only in the AES. CRYP_IV0LR (address offset: 0x40) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 IV0 IV1 IV2 IV3 IV4 IV5 IV6 IV7 IV8 IV9 IV10 IV11 IV12 IV13 IV14 IV15 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 IV16 IV17 IV18 IV19 IV20 IV21 IV22 IV23 IV24 IV25 IV26 IV27 IV28 IV29 IV30 IV31 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw CRYP_IV0RR (address offset: 0x44) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 IV32 IV33 IV34 IV35 IV36 IV37 IV38 IV39 IV40 IV41 IV42 IV43 IV44 IV45 IV46 IV47 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 IV48 IV49 IV50 IV51 IV52 IV53 IV54 IV55 IV56 IV57 IV58 IV59 IV60 IV61 IV62 IV63 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw k3.41 b23 k3.57 b7 583/1416 Doc ID 018909 Rev 3 k3.42 b22 k3.58 b6 k3.43 b21 k3.59 b5 k3.44 b20 k3.60 b4 k3.45 b19 k3.61 b3 k3.46 b18 k3.62 b2 k3.47 b17 k3.63 b1 k3.48 b16 k3.64 b0
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RM0090 Reference manual STM32F40x,
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Contents RM0090 3.5.3 Erase . . . .
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Contents RM0090 6.3.1 RCC clock con
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Contents RM0090 7.4.7 GPIO port bit
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Contents RM0090 10.3.4 Falling trig
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Contents RM0090 12.4.2 Independent
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Contents RM0090 14.3.3 Repetition c
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Contents RM0090 15.4.12 TIMx auto-r
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Contents RM0090 17.4.6 TIM6&TIM7 co
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Contents RM0090 22.1 HASH introduct
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Contents RM0090 24.3.3 Tx mailboxes
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Contents RM0090 26.3.14 Hardware fl
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Contents RM0090 28.4.13 SD I/O mode
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Contents RM0090 29.7 Ethernet inter
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Contents RM0090 31.3.1 High-speed O
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Contents RM0090 33.2 Reference ARM
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List of tables RM0090 List of table
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List of tables RM0090 Table 98. Tra
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List of tables RM0090 Table 192. NO
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List of figures RM0090 Figure 49. A
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List of figures RM0090 Figure 151.
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Documentation conventions RM0090 1
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Memory and bus architecture RM0090
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CRC calculation unit RM0090 4 CRC c
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CRC calculation unit RM0090 Bits 7:
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Power control (PWR) RM0090 Figure 7
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Power control (PWR) RM0090 When the
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Power control (PWR) RM0090 mode (se
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Power control (PWR) RM0090 A PVDO f
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Power control (PWR) RM0090 5.3.3 Sl
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Power control (PWR) RM0090 If an ac
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Power control (PWR) RM0090 I/O stat
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Power control (PWR) RM0090 Safe RTC
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Power control (PWR) RM0090 Bit 4 PV
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Power control (PWR) RM0090 5.4.3 PW
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DMA controller (DMA) RM0090 9 DMA c
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DMA controller (DMA) RM0090 9.3 DMA
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DMA controller (DMA) RM0090 Figure
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DMA controller (DMA) RM0090 Table 3
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DMA controller (DMA) RM0090 In dire
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DMA controller (DMA) RM0090 memory
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DMA controller (DMA) RM0090 9.3.11
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DMA controller (DMA) RM0090 9.4 DMA
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DMA controller (DMA) RM0090 9.5.5 D
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Interrupts and events RM0090 Table
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Basic timers (TIM6&TIM7) RM0090 17
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Basic timers (TIM6&TIM7) RM0090 17.
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Flexible static memory controller (
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Debug support (DBG) RM0090 33 Debug
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Debug support (DBG) RM0090 Figure 4
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Debug support (DBG) RM0090 33.4.3 I
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Debug support (DBG) RM0090 Figure 4
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Debug support (DBG) RM0090 Only the
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Debug support (DBG) RM0090 Table 22
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Debug support (DBG) RM0090 Note: No
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Debug support (DBG) RM0090 33.9 AHB
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Debug support (DBG) RM0090 33.11 Ca
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Debug support (DBG) RM0090 For this
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Debug support (DBG) RM0090 33.15.3
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Debug support (DBG) RM0090 31 30 29
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Debug support (DBG) RM0090 Bit 20:1
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Device electronic signature RM0090
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A ADC_CCR . . . . . . . . . . . . .
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DMA_SxM1AR . . . . . . . . . . . .
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HASH_SR . . . . . . . . . . . . . .
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RNG_DR . . . . . . . . . . . . . .
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Revision history RM0090 Revision hi
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Revision history RM0090 Table 238.
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RM0090: Reference manual - STMicroelectronics

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