RM0090: Reference manual - STMicroelectronics

RM0090 Serial peripheral interface (SPI)
I2Sx can operate in master mode. As a result:
● Only I2Sx can output SCK and WS in half duplex mode
● Only I2Sx can deliver SCK and WS to I2S2_ext and I2S3_ext in full duplex mode.
The extended I2Ss (I2Sx_ext) can be used only in full duplex mode. The I2Sx_ext operate
always in slave mode.
Both I2Sx and I2Sx_ext can be configured as transmitters or receivers.
27.4.3 Supported audio protocols
The four-line bus has to handle only audio data generally time-multiplexed on two channels:
the right channel and the left channel. However there is only one 16-bit register for the
transmission and the reception. So, it is up to the software to write into the data register the
adequate value corresponding to the considered channel side, or to read the data from the
data register and to identify the corresponding channel by checking the CHSIDE bit in the
SPI_SR register. Channel Left is always sent first followed by the channel right (CHSIDE
has no meaning for the PCM protocol).
Four data and packet frames are available. Data may be sent with a format of:
● 16-bit data packed in 16-bit frame
● 16-bit data packed in 32-bit frame
● 24-bit data packed in 32-bit frame
● 32-bit data packed in 32-bit frame
When using 16-bit data extended on 32-bit packet, the first 16 bits (MSB) are the significant
bits, the 16-bit LSB is forced to 0 without any need for software action or DMA request (only
one read/write operation).
The 24-bit and 32-bit data frames need two CPU read or write operations to/from the
SPI_DR or two DMA operations if the DMA is preferred for the application. For 24-bit data
frame specifically, the 8 nonsignificant bits are extended to 32 bits with 0-bits (by hardware).
For all data formats and communication standards, the most significant bit is always sent
first (MSB first).
The I 2 S interface supports four audio standards, configurable using the I2SSTD[1:0] and
PCMSYNC bits in the SPI_I2SCFGR register.
I 2 S Philips standard
For this standard, the WS signal is used to indicate which channel is being transmitted. It is
activated one CK clock cycle before the first bit (MSB) is available.
Doc ID 018909 Rev 3 818/1416