RM0090: Reference manual - STMicroelectronics

Embedded Flash memory interface RM0090
Figure 4. Sequential 32-bit instruction execution
@
1
WAIT
@
F
1
D
1
F
E
1
D E
Without prefetch
2 2 2 2
@ F D E
3 3 3 3
@ F D E
4 4 4 4
@
5
WAIT
F
5
D
5
E
5
@
F D E
6 6 6 6
@ F D
7 7 7
@ F
8 8
ins 1
fetch
ins 2
fetch
ins 3
fetch
ins 4
fetch
Read ins 1, 2, 3, 4 Gives ins 1, 2, 3, 4 Read ins 5, 6, 7, 8 Gives ins 5, 6, 7, 8
@
1
Wait data F
1
D
1
E
1
@
F D E
2 2 2 2
@ F D
3 3 3
@ F
4 4
@
5
ins 1 ins 2
fetch fetch
When the code is not sequential (branch), the instruction may not be present in the currently
used instruction line or in the prefetched instruction line. In this case (miss), the penalty in
terms of number of cycles is at least equal to the number of wait states.
65/1416 Doc ID 018909 Rev 3
ins 5
fetch
E
3
D E
4 4
F D E
5 5 5
@ F D E
6 6 6
@ F D
7 7 7
@ F
8 8
Read ins 1, 2, 3, 4 Gives ins 1, 2, 3, 4 Gives ins 5, 6, 7, 8
Read ins 5, 6, 7, 8 Read ins 9, 10, ...
ins 6
fetch
ins 3 ins 4 ins 5 ins 6 ins 7 ins 8
fetch fetch fetch fetch fetch fetch
ins 7
fetch
With prefetch
@
ins 8
fetch
Cortex-M3 pipeline
AHB protocol
F D E
@ : address requested
F: Fetch stage
D: Decode stage
E: Execute stage
ai16005