RM0090: Reference manual - STMicroelectronics

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<strong>RM0090</strong> Controller area network (bxCAN) 31 Table 100. bxCAN register map and reset values (continued) Offset Register 0x200 0x204 CAN_FMR Reserved CAN2SB[5:0] Reserved Reset value 0 0 1 1 1 0 1 CAN_FM1R Reserved FBM[27:0] Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x208 Reserved 0x20C CAN_FS1R Reserved FSC[27:0] Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x210 Reserved 0x214 CAN_FFA1R Reserved FFA[27:0] Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x218 Reserved 0x21C CAN_FA1R Reserved FACT[27:0] Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x220 Reserved 0x224- 0x23F 0x240 0x244 0x248 0x24C . . . . 0x318 0x31C Reserved CAN_F0R1 FB[31:0] Reset value x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x CAN_F0R2 FB[31:0] Reset value x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x CAN_F1R1 FB[31:0] Reset value x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x CAN_F1R2 FB[31:0] Reset value x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x . . . . 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CAN_F27R1 FB[31:0] Reset value x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x CAN_F27R2 FB[31:0] Reset value x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x . . . . Doc ID 018909 Rev 3 702/1416 FINIT
Inter-integrated circuit (I 2 C) interface <strong>RM0090</strong> 25 Inter-integrated circuit (I 2 C) interface This section applies to the whole STM32F4xx family, unless otherwise specified. 25.1 I 2 C introduction I 2 C (inter-integrated circuit) bus Interface serves as an interface between the microcontroller and the serial I 2 C bus. It provides multimaster capability, and controls all I 2 C bus-specific sequencing, protocol, arbitration and timing. It supports standard and fast speed modes. It is also SMBus 2.0 compatible. It may be used for a variety of purposes, including CRC generation and verification, SMBus (system management bus) and PMBus (power management bus). Depending on specific device implementation DMA capability can be available for reduced CPU overload. 25.2 I 2 C main features ● Parallel-bus/I2C protocol converter ● Multimaster capability: the same interface can act as Master or Slave ● I2C Master features: – Clock generation – Start and Stop generation ● I2C Slave features: – Programmable I2C Address detection – Dual Addressing Capability to acknowledge 2 slave addresses – Stop bit detection ● Generation and detection of 7-bit/10-bit addressing and General Call ● Supports different communication speeds: – Standard Speed (up to 100 kHz) – Fast Speed (up to 400 kHz) ● Programmable digital noise filter for STM32F42x and STM32F43x ● Status flags: – Transmitter/Receiver mode flag – End-of-Byte transmission flag – I2C busy flag ● Error flags: – Arbitration lost condition for master mode – Acknowledgement failure after address/ data transmission – Detection of misplaced start or stop condition – Overrun/Underrun if clock stretching is disabled ● 2 Interrupt vectors: – 1 Interrupt for successful address/ data communication 703/1416 Doc ID 018909 Rev 3
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RM0090 Reference manual STM32F40x,
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Contents RM0090 3.5.3 Erase . . . .
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Contents RM0090 33.2 Reference ARM
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List of tables RM0090 List of table
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List of tables RM0090 Table 98. Tra
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Documentation conventions RM0090 1
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Memory and bus architecture RM0090
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Device electronic signature RM0090
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A ADC_CCR . . . . . . . . . . . . .
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DMA_SxM1AR . . . . . . . . . . . .
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RNG_DR . . . . . . . . . . . . . .
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Revision history RM0090 Revision hi
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