RM0090: Reference manual - STMicroelectronics

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<strong>RM0090</strong> Inter-integrated circuit (I 2 C) interface – 1 Interrupt for error condition ● Optional clock stretching ● 1-byte buffer with DMA capability ● Configurable PEC (packet error checking) generation or verification: – PEC value can be transmitted as last byte in Tx mode – PEC error checking for last received byte ● SMBus 2.0 Compatibility: – 25 ms clock low timeout delay – 10 ms master cumulative clock low extend time – 25 ms slave cumulative clock low extend time – Hardware PEC generation/verification with ACK control – Address Resolution Protocol (ARP) supported ● PMBus Compatibility Note: Some of the above features may not be available in certain products. The user should refer to the product data sheet, to identify the specific features supported by the I 2 C interface implementation. 25.3 I 2 C functional description In addition to receiving and transmitting data, this interface converts it from serial to parallel format and vice versa. The interrupts are enabled or disabled by software. The interface is connected to the I 2 C bus by a data pin (SDA) and by a clock pin (SCL). It can be connected with a standard (up to 100 kHz) or fast (up to 400 kHz) I 2 C bus. 25.3.1 Mode selection The interface can operate in one of the four following modes: ● Slave transmitter ● Slave receiver ● Master transmitter ● Master receiver By default, it operates in slave mode. The interface automatically switches from slave to master, after it generates a START condition and from master to slave, if an arbitration loss or a Stop generation occurs, allowing multimaster capability. Communication flow In Master mode, the I 2 C interface initiates a data transfer and generates the clock signal. A serial data transfer always begins with a start condition and ends with a stop condition. Both start and stop conditions are generated in master mode by software. In Slave mode, the interface is capable of recognizing its own addresses (7 or 10-bit), and the General Call address. The General Call address detection may be enabled or disabled by software. Data and addresses are transferred as 8-bit bytes, MSB first. The first byte(s) following the start condition contain the address (one in 7-bit mode, two in 10-bit mode). The address is always transmitted in Master mode. Doc ID 018909 Rev 3 704/1416
Inter-integrated circuit (I 2 C) interface <strong>RM0090</strong> A 9th clock pulse follows the 8 clock cycles of a byte transfer, during which the receiver must send an acknowledge bit to the transmitter. Refer to Figure 238. Figure 238. I 2 C bus protocol SDA SCL Start condition MSB Acknowledge may be enabled or disabled by software. The I 2 C interface addresses (dual addressing 7-bit/ 10-bit and/or general call address) can be selected by software. The block diagram of the I 2 C interface is shown in Figure 239. 705/1416 Doc ID 018909 Rev 3 1 2 8 9 ACK Stop condition
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RM0090 Reference manual STM32F40x,
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Contents RM0090 3.5.3 Erase . . . .
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Contents RM0090 6.3.1 RCC clock con
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Contents RM0090 12.4.2 Independent
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Contents RM0090 31.3.1 High-speed O
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Contents RM0090 33.2 Reference ARM
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List of tables RM0090 List of table
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List of tables RM0090 Table 98. Tra
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List of tables RM0090 Table 192. NO
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List of figures RM0090 Figure 49. A
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List of figures RM0090 Figure 151.
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Documentation conventions RM0090 1
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Memory and bus architecture RM0090
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Power control (PWR) RM0090 Figure 7
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Power control (PWR) RM0090 When the
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Power control (PWR) RM0090 mode (se
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Power control (PWR) RM0090 A PVDO f
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Power control (PWR) RM0090 5.3.3 Sl
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Power control (PWR) RM0090 If an ac
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Power control (PWR) RM0090 I/O stat
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Power control (PWR) RM0090 Safe RTC
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Power control (PWR) RM0090 Bit 4 PV
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Power control (PWR) RM0090 5.4.3 PW
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DMA controller (DMA) RM0090 9 DMA c
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DMA controller (DMA) RM0090 9.3 DMA
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DMA controller (DMA) RM0090 Figure
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DMA controller (DMA) RM0090 Table 3
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DMA controller (DMA) RM0090 In dire
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DMA controller (DMA) RM0090 Figure
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DMA controller (DMA) RM0090 memory
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DMA controller (DMA) RM0090 9.3.11
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DMA controller (DMA) RM0090 9.4 DMA
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DMA controller (DMA) RM0090 Bits 25
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DMA controller (DMA) RM0090 9.5.5 D
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DMA controller (DMA) RM0090 Bits 8
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DMA controller (DMA) RM0090 15 14 1
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Interrupts and events RM0090 Table
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Basic timers (TIM6&TIM7) RM0090 17.
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Window watchdog (WWDG) RM0090 19.6
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Window watchdog (WWDG) RM0090 19.6.
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Hash processor (HASH) RM0090 with v
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Hash processor (HASH) RM0090 Proced
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Hash processor (HASH) RM0090 Bit 12
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Hash processor (HASH) RM0090 22.4.2
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Hash processor (HASH) RM0090 Bit 3
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Real-time clock (RTC) RM0090 23.2 R
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Debug support (DBG) RM0090 33 Debug
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Debug support (DBG) RM0090 31 30 29
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Device electronic signature RM0090
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A ADC_CCR . . . . . . . . . . . . .
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DMA_SxM1AR . . . . . . . . . . . .
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HASH_SR . . . . . . . . . . . . . .
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RNG_DR . . . . . . . . . . . . . .
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Revision history RM0090 Revision hi
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Revision history RM0090 Table 238.
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