RM0090: Reference manual - STMicroelectronics

Universal synchronous asynchronous receiver transmitter (USART) RM0090
has been written). This means that it is not possible to receive a synchronous data without
transmitting data.
The LBCL, CPOL and CPHA bits have to be selected when both the transmitter and the
receiver are disabled (TE=RE=0) to ensure that the clock pulses function correctly. These
bits should not be changed while the transmitter or the receiver is enabled.
It is advised that TE and RE are set in the same instruction in order to minimize the setup
and the hold time of the receiver.
The USART supports master mode only: it cannot receive or send data related to an input
clock (SCLK is always an output).
Figure 256. USART example of synchronous transmission
USART
Figure 257. USART data clock timing diagram (M=0)
Idle or preceding
transmission
Clock (CPOL=0, CPHA=0)
Clock (CPOL=0, CPHA=1)
Clock (CPOL=1, CPHA=0)
Clock (CPOL=1, CPHA=1)
Data on TX
(from master)
Start
767/1416 Doc ID 018909 Rev 3
RX
TX
SCLK
Data out
Data in
Synchronous device
(e.g. slave SPI)
Clock
M=0 (8 data bits)
0 1 2 3 4 5 6 7
Stop
Start LSB MSB Stop
Data on RX 0 1 2 3 4 5 6 7
(from slave)
LSB
MSB
Capture Strobe
*
*
*
*
*
Idle or next
transmission
* LBCL bit controls last data clock pulse