RM0090: Reference manual - STMicroelectronics

Ethernet (ETH): media access control (MAC) with DMA controller RM0090
Figure 348. TxDMA operation in OSF mode
No
No
Poll
demand
TxDMA suspended
Previous frame
status available
Time stamp
present?
Yes
Write time stamp to
TDES2 & TDES3
for previous frame
(AHB)
error?
No
Write status word to
prev. frame’s TDES0
(AHB)
error?
Transmit frame processing
The transmit DMA expects that the data buffers contain complete Ethernet frames,
excluding preamble, pad bytes, and FCS fields. The DA, SA, and Type/Len fields contain
valid data. If the transmit descriptor indicates that the MAC core must disable CRC or pad
insertion, the buffer must have complete Ethernet frames (excluding preamble), including
the CRC bytes. Frames can be data-chained and span over several buffers. Frames have to
be delimited by the first descriptor (TDES0[28]) and the last descriptor (TDES0[29]). As the
transmission starts, TDES0[28] has to be set in the first descriptor. When this occurs, the
frame data are transferred from the memory buffer to the Transmit FIFO. Concurrently, if the
last descriptor (TDES0[29]) of the current frame is cleared, the transmit process attempts to
acquire the next descriptor. The transmit process expects TDES0[28] to be cleared in this
descriptor. If TDES0[29] is cleared, it indicates an intermediary buffer. If TDES0[29] is set, it
947/1416 Doc ID 018909 Rev 3
Yes
Yes
No
No
Close intermediate
descriptor
No
Start TxDMA
(Re-)fetch next
descriptor
(AHB)
error?
No
Own
bit set?
Yes
Transfer data from
buffer(s)
(AHB)
error?
No
Frame xfer
complete?
Time stamp
present?
No
Write status word to
prev. frame’s TDES0
(AHB)
error?
Yes
Start
Yes
Yes
Yes
Yes
No
Stop TxDMA
No
Second
frame?
Yes
Wait for previous
frame’s Tx status
Write time stamp to
TDES2 & TDES3
for previous frame
(AHB)
error?
Yes
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