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<strong>RM0090</strong> DMA controller (DMA) Table 42. DMA register map and reset values (continued) Offset Register 0x0034 0x0038 0x003C 0x0040 DMA_S1M0AR M0A[31:0] Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DMA_S1M1AR M1A[31:0] Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DMA_S1FCR Reserved FEIE Doc ID 018909 Rev 3 244/1416 Reserved FS[2:0] Reset value 0 1 0 0 0 0 1 DMA_S2CR Reserved CHSEL [2:0] MBURST[1:0] PBURST[1:0] ACK CT DBM PL[1:0] PINCOS MSIZE[1:0] PSIZE[1:0] MINC PINC CIRC DMDIS FTH [1:0] DIR [1:0] PFCTRL TCIE HTIE TEIE DMEIE EN Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x0044 DMA_S2NDTR Reset value Reserved 0 0 0 0 0 0 NDT[15:.] 0 0 0 0 0 0 0 0 0 0 0x0048 0x004C 0x0050 0x0054 0x0058 DMA_S2PAR PA[31:0] Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DMA_S2M0AR M0A[31:0] Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DMA_S2M1AR M1A[31:0] Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DMA_S2FCR Reserved FEIE Reserved FS[2:0] Reset value 0 1 0 0 0 0 1 DMA_S3CR Reserved CHSEL[2:0] MBURST[1:0] PBURST[1:0] ACK CT DBM PL[1:0] PINCOS MSIZE[1:0] PSIZE[1:0] MINC PINC CIRC DIR[1:0] DMDIS FTH [1:0] PFCTRL TCIE HTIE TEIE DMEIE EN Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x005C DMA_S3NDTR Reset value Reserved 0 0 0 0 0 0 NDT[15:.] 0 0 0 0 0 0 0 0 0 0 0x0060 0x0064 0x0068 0x006C DMA_S3PAR PA[31:0] Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DMA_S3M0AR M0A[31:0] Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DMA_S3M1AR M1A[31:0] Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DMA_S3FCR 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved FEIE Reserved FS[2:0] Reset value 0 1 0 0 0 0 1 DMDIS FTH [1:0]
DMA controller (DMA) <strong>RM0090</strong> Table 42. DMA register map and reset values (continued) Offset Register 0x0070 DMA_S4CR Reserved 245/1416 Doc ID 018909 Rev 3 CHSEL[2:0] MBURST[1:0] PBURST[1:0] ACK CT DBM PL[1:0] PINCOS MSIZE[1:0] PSIZE[1:0] MINC PINC CIRC DIR [1:0] PFCTRL TCIE HTIE TEIE DMEIE EN Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x0074 DMA_S4NDTR Reset value Reserved 0 0 0 0 0 0 NDT[15:.] 0 0 0 0 0 0 0 0 0 0 0x0078 DMA_S4PAR Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PA[31:0] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x007C DMA_S4M0AR Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 M0A[31:0] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x0080 DMA_S4M1AR Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 M1A[31:0] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x0084 0x0088 DMA_S4FCR Reserved FEIE Reserved FS[2:0] Reset value 0 1 0 0 0 0 1 DMA_S5CR Reserved CHSEL[2:0] MBURST[1:0] PBURST[1:0] ACK CT DBM PL[1:0] PINCOS MSIZE[1:0] PSIZE[1:0] MINC PINC CIRC DIR[1:0] DMDIS FTH [1:0] PFCTRL TCIE HTIE TEIE DMEIE EN Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x008C DMA_S5NDTR Reset value Reserved 0 0 0 0 0 0 NDT[15:.] 0 0 0 0 0 0 0 0 0 0 0x0090 DMA_S5PAR Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PA[31:0] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x0094 DMA_S5M0AR Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 M0A[31:0] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x0098 DMA_S5M1AR Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 M1A[31:0] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x009C 0x00A0 FEIE DMA_S5FCR Reserved FS[2:0] FTH [1:0] Reset value 0 1 0 0 0 0 1 DMA_S6CR Reserved CHSEL[2:0] MBURST[1:0] PBURST[1:0] ACK CT DBM PL[1:0] PINCOS MSIZE[1:0] PSIZE[1:0] MINC PINC CIRC DIR[1:0] Reserved DMDIS PFCTRL TCIE HTIE TEIE DMEIE EN Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x00A4 DMA_S6NDTR Reset value Reserved 0 0 0 0 0 0 NDT[15:.] 0 0 0 0 0 0 0 0 0 0 0x00A8 DMA_S6PAR Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PA[31:0] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x00AC DMA_S6M0AR Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 M0A[31:0] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x00B0 DMA_S6M1AR Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 M1A[31:0] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x00B4 DMA_S6FCR 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved FEIE Reserved FS[2:0] Reset value 0 1 0 0 0 0 1 DMDIS FTH [1:0]
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RM0090 Reference manual STM32F40x,
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Contents RM0090 3.5.3 Erase . . . .
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Contents RM0090 6.3.1 RCC clock con
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Contents RM0090 7.4.7 GPIO port bit
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Contents RM0090 10.3.4 Falling trig
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Contents RM0090 12.4.2 Independent
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Contents RM0090 14.3.3 Repetition c
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Contents RM0090 15.4.12 TIMx auto-r
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Contents RM0090 17.4.6 TIM6&TIM7 co
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Contents RM0090 22.1 HASH introduct
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Contents RM0090 24.3.3 Tx mailboxes
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Contents RM0090 26.3.14 Hardware fl
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Contents RM0090 28.4.13 SD I/O mode
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Contents RM0090 29.7 Ethernet inter
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Contents RM0090 31.3.1 High-speed O
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Contents RM0090 33.2 Reference ARM
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List of tables RM0090 List of table
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List of tables RM0090 Table 98. Tra
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List of tables RM0090 Table 192. NO
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List of figures RM0090 Figure 49. A
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List of figures RM0090 Figure 151.
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Documentation conventions RM0090 1
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Memory and bus architecture RM0090
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Embedded Flash memory interface RM0
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CRC calculation unit RM0090 4 CRC c
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CRC calculation unit RM0090 Bits 7:
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Power control (PWR) RM0090 Figure 7
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Power control (PWR) RM0090 When the
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Power control (PWR) RM0090 mode (se
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Power control (PWR) RM0090 A PVDO f
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Power control (PWR) RM0090 5.3.3 Sl
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Power control (PWR) RM0090 If an ac
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Power control (PWR) RM0090 I/O stat
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Power control (PWR) RM0090 Safe RTC
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Power control (PWR) RM0090 Bit 4 PV
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Power control (PWR) RM0090 5.4.3 PW
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Reset and clock control for (RCC) R
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General-purpose I/Os (GPIO) RM0090
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Basic timers (TIM6&TIM7) RM0090 17
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Basic timers (TIM6&TIM7) RM0090 Fig
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Basic timers (TIM6&TIM7) RM0090 17.
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Independent watchdog (IWDG) RM0090
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Independent watchdog (IWDG) RM0090
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Window watchdog (WWDG) RM0090 19 Wi
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Window watchdog (WWDG) RM0090 case,
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Window watchdog (WWDG) RM0090 19.6
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Window watchdog (WWDG) RM0090 19.6.
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Random number generator (RNG) RM009
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Hash processor (HASH) RM0090 22.3 H
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Hash processor (HASH) RM0090 has le
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Hash processor (HASH) RM0090 The le
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Hash processor (HASH) RM0090 with v
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Hash processor (HASH) RM0090 Proced
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Hash processor (HASH) RM0090 Bit 12
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Hash processor (HASH) RM0090 22.4.2
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Hash processor (HASH) RM0090 Bit 3
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Hash processor (HASH) RM0090 Table
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Real-time clock (RTC) RM0090 23.2 R
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Flexible static memory controller (
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Debug support (DBG) RM0090 33 Debug
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Debug support (DBG) RM0090 Figure 4
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Debug support (DBG) RM0090 33.4.3 I
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Debug support (DBG) RM0090 Figure 4
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Debug support (DBG) RM0090 Only the
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Debug support (DBG) RM0090 Table 22
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Debug support (DBG) RM0090 Note: No
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Debug support (DBG) RM0090 33.9 AHB
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Debug support (DBG) RM0090 33.11 Ca
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Debug support (DBG) RM0090 For this
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Debug support (DBG) RM0090 33.15.3
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Debug support (DBG) RM0090 31 30 29
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Debug support (DBG) RM0090 Bit 20:1
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Device electronic signature RM0090
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A ADC_CCR . . . . . . . . . . . . .
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DMA_SxM1AR . . . . . . . . . . . .
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HASH_SR . . . . . . . . . . . . . .
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RNG_DR . . . . . . . . . . . . . .
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Revision history RM0090 Revision hi
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Revision history RM0090 Table 238.
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RM0090: Reference manual - STMicroelectronics

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