RM0090: Reference manual - STMicroelectronics

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<strong>RM0090</strong> Serial peripheral interface (SPI) 27.5.6 SPI RX CRC register (SPI_RXCRCR) (not used in I 2 S mode) Address offset: 0x14 Reset value: 0x0000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RXCRC[15:0] r r r r r r r r r r r r r r r r Bits 15:0 RXCRC[15:0]: Rx CRC register When CRC calculation is enabled, the RxCRC[15:0] bits contain the computed CRC value of the subsequently received bytes. This register is reset when the CRCEN bit in SPI_CR1 register is written to 1. The CRC is calculated serially using the polynomial programmed in the SPI_CRCPR register. Only the 8 LSB bits are considered when the data frame format is set to be 8-bit data (DFF bit of SPI_CR1 is cleared). CRC calculation is done based on any CRC8 standard. The entire 16-bits of this register are considered when a 16-bit data frame format is selected (DFF bit of the SPI_CR1 register is set). CRC calculation is done based on any CRC16 standard. Note: A read to this register when the BSY Flag is set could return an incorrect value. Not used for I 2 S mode. 27.5.7 SPI TX CRC register (SPI_TXCRCR) (not used in I 2 S mode) Address offset: 0x18 Reset value: 0x0000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TXCRC[15:0] r r r r r r r r r r r r r r r r Bits 15:0 TXCRC[15:0]: Tx CRC register When CRC calculation is enabled, the TxCRC[7:0] bits contain the computed CRC value of the subsequently transmitted bytes. This register is reset when the CRCEN bit of SPI_CR1 is written to 1. The CRC is calculated serially using the polynomial programmed in the SPI_CRCPR register. Only the 8 LSB bits are considered when the data frame format is set to be 8-bit data (DFF bit of SPI_CR1 is cleared). CRC calculation is done based on any CRC8 standard. The entire 16-bits of this register are considered when a 16-bit data frame format is selected (DFF bit of the SPI_CR1 register is set). CRC calculation is done based on any CRC16 standard. Note: A read to this register when the BSY flag is set could return an incorrect value. Not used for I 2 S mode. Doc ID 018909 Rev 3 838/1416
Serial peripheral interface (SPI) <strong>RM0090</strong> 27.5.8 SPI_I 2 S configuration register (SPI_I2SCFGR) Address offset: 0x1C Reset value: 0x0000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved I2SMOD I2SE I2SCFG PCMSY NC Reserved I2SSTD CKPOL DATLEN CHLEN rw rw rw rw rw rw rw rw rw rw rw Bits 15:12 Reserved, must be kept at reset value. Bit 11 I2SMOD: I2S mode selection 0: SPI mode is selected 1: I2S mode is selected Note: This bit should be configured when the SPI or I 2 S is disabled Bit 10 I2SE: I2S Enable 0: I 2 S peripheral is disabled 1: I 2 S peripheral is enabled Note: Not used in SPI mode Bit 9:8 I2SCFG: I2S configuration mode 00: Slave - transmit 01: Slave - receive 10: Master - transmit 11: Master - receive Note: This bit should be configured when the I 2 S is disabled. Not used in SPI mode Bit 7 PCMSYNC: PCM frame synchronization 0: Short frame synchronization 1: Long frame synchronization Note: This bit has a meaning only if I2SSTD = 11 (PCM standard is used) Not used in SPI mode Bit 6 Reserved: forced at 0 by hardware Bit 5:4 I2SSTD: I2S standard selection 00: I 2 S Philips standard. 01: MSB justified standard (left justified) 10: LSB justified standard (right justified) 11: PCM standard For more details on I 2 S standards, refer to Section 27.4.3 on page 818. Not used in SPI mode. Note: For correct operation, these bits should be configured when the I 2 S is disabled. Bit 3 CKPOL: Steady state clock polarity 0: I 2 S clock steady state is low level 1: I 2 S clock steady state is high level Note: For correct operation, this bit should be configured when the I 2 S is disabled. Not used in SPI mode 839/1416 Doc ID 018909 Rev 3
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RM0090 Reference manual STM32F40x,
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Contents RM0090 3.5.3 Erase . . . .
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Contents RM0090 6.3.1 RCC clock con
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Contents RM0090 7.4.7 GPIO port bit
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Contents RM0090 10.3.4 Falling trig
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Contents RM0090 12.4.2 Independent
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Contents RM0090 14.3.3 Repetition c
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Contents RM0090 15.4.12 TIMx auto-r
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Contents RM0090 17.4.6 TIM6&TIM7 co
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Contents RM0090 22.1 HASH introduct
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Contents RM0090 24.3.3 Tx mailboxes
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Contents RM0090 26.3.14 Hardware fl
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Contents RM0090 28.4.13 SD I/O mode
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Contents RM0090 29.7 Ethernet inter
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Contents RM0090 31.3.1 High-speed O
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Contents RM0090 33.2 Reference ARM
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List of tables RM0090 List of table
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List of tables RM0090 Table 98. Tra
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List of tables RM0090 Table 192. NO
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List of figures RM0090 Figure 49. A
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List of figures RM0090 Figure 151.
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Documentation conventions RM0090 1
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Memory and bus architecture RM0090
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Embedded Flash memory interface RM0
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CRC calculation unit RM0090 4 CRC c
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CRC calculation unit RM0090 Bits 7:
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Power control (PWR) RM0090 Figure 7
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Power control (PWR) RM0090 When the
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Power control (PWR) RM0090 mode (se
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Power control (PWR) RM0090 A PVDO f
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Power control (PWR) RM0090 5.3.3 Sl
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Power control (PWR) RM0090 If an ac
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Power control (PWR) RM0090 I/O stat
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Power control (PWR) RM0090 Safe RTC
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Power control (PWR) RM0090 Bit 4 PV
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Power control (PWR) RM0090 5.4.3 PW
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Reset and clock control for (RCC) R
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DMA controller (DMA) RM0090 9 DMA c
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DMA controller (DMA) RM0090 9.3 DMA
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DMA controller (DMA) RM0090 Figure
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DMA controller (DMA) RM0090 Table 3
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DMA controller (DMA) RM0090 In dire
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DMA controller (DMA) RM0090 Figure
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DMA controller (DMA) RM0090 memory
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DMA controller (DMA) RM0090 9.3.11
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DMA controller (DMA) RM0090 9.4 DMA
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DMA controller (DMA) RM0090 Bits 25
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DMA controller (DMA) RM0090 9.5.5 D
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DMA controller (DMA) RM0090 Bits 8
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DMA controller (DMA) RM0090 15 14 1
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Interrupts and events RM0090 10 Int
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Interrupts and events RM0090 Table
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Interrupts and events RM0090 genera
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Interrupts and events RM0090 10.3 E
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Interrupts and events RM0090 15 14
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Basic timers (TIM6&TIM7) RM0090 17
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Basic timers (TIM6&TIM7) RM0090 Fig
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Basic timers (TIM6&TIM7) RM0090 17.
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Independent watchdog (IWDG) RM0090
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Independent watchdog (IWDG) RM0090
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Window watchdog (WWDG) RM0090 19 Wi
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Window watchdog (WWDG) RM0090 case,
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Window watchdog (WWDG) RM0090 19.6
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Window watchdog (WWDG) RM0090 19.6.
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Cryptographic processor (CRYP) RM00
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Hash processor (HASH) RM0090 22.3 H
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Hash processor (HASH) RM0090 has le
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Hash processor (HASH) RM0090 The le
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Hash processor (HASH) RM0090 with v
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Hash processor (HASH) RM0090 Proced
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Hash processor (HASH) RM0090 Bit 12
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Hash processor (HASH) RM0090 22.4.2
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Hash processor (HASH) RM0090 Bit 3
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Hash processor (HASH) RM0090 HASH_H
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Hash processor (HASH) RM0090 Table
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Real-time clock (RTC) RM0090 23.2 R
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Real-time clock (RTC) RM0090 The as
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Real-time clock (RTC) RM0090 23.3.5
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Real-time clock (RTC) RM0090 RTC_TR
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Real-time clock (RTC) RM0090 window
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Real-time clock (RTC) RM0090 Bit 3
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Controller area network (bxCAN) RM0
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Debug support (DBG) RM0090 33 Debug
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Debug support (DBG) RM0090 Figure 4
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Debug support (DBG) RM0090 33.4.3 I
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Debug support (DBG) RM0090 Only the
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Debug support (DBG) RM0090 Note: No
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Debug support (DBG) RM0090 33.9 AHB
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Debug support (DBG) RM0090 31 30 29
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Debug support (DBG) RM0090 Bit 20:1
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Device electronic signature RM0090
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A ADC_CCR . . . . . . . . . . . . .
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DMA_SxM1AR . . . . . . . . . . . .
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HASH_SR . . . . . . . . . . . . . .
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RNG_DR . . . . . . . . . . . . . .
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Revision history RM0090 Revision hi
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Revision history RM0090 Table 238.
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