RM0090: Reference manual - STMicroelectronics

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<strong>RM0090</strong> General-purpose I/Os (GPIO) Figure 18. Selecting an alternate function on STM32F40x and STM32F41x 1. Configured in FS. For pins 0 to 7, the GPIOx_AFRL[31:0] register selects the dedicated alternate function AF0 (system) AF1 (TIM1/TIM2) AF2 (TIM3..5) AF3 (TIM8..11) AF4 (I2C1..3) AF5 (SPI1/SPI2) AF6 (SPI3) AF7 (USART1..3) AF8 (USART4..6) AF9 (CAN1/CAN2, TIM12..14) AF10 (OTG_FS, OTG_HS) AF11 (ETH) AF12 (FSMC, SDIO, OTG_HS (1) ) AF13 (DCMI) AF14 AF15 (EVENTOUT) AFRL[31:0] Pin x (x = 0..7) For pins 8 to 15, the GPIOx_AFRH[31:0] register selects the dedicated alternate function AF0 (system) AF1 (TIM1/TIM2) AF2 (TIM3..5) AF3 (TIM8..11) AF4 (I2C1..3) AF5 (SPI1/SPI2) AF6 (SPI3) AF7 (USART1..3) AF8 (USART4..6) AF9 (CAN1/CAN2, TIM12..14) AF10 (OTG_FS, OTG_HS) AF11 (ETH) AF12 (FSMC, SDIO, OTG_HS (1) ) AF13 (DCMI) AF14 AF15 (EVENTOUT) 1 Pin x (x = 8..15) 1 AFRH[31:0] ai17538 Doc ID 018909 Rev 3 190/1416
General-purpose I/Os (GPIO) <strong>RM0090</strong> Figure 19. Selecting an alternate function on STM32F42x and STM32F43x For pins 0 to 7, the GPIOx_AFRL[31:0] register selects the dedicated alternate function AF0 (system) AF1 (TIM1/TIM2) AF2 (TIM3..5) AF3 (TIM8..11) AF4 (I2C1..3) AF5 (SPI1/2/4/5/6) AF6 (SPI3) AF7 (USART1..3) AF8 (USART4..8) AF9 (CAN1/CAN2, TIM12..14) AF10 (OTG_FS, OTG_HS) AF11 (ETH) AF12 (FSMC, SDIO, OTG_HS (1) ) AF13 (DCMI) AF14 AF15 (EVENTOUT) 1. Configured in FS. 7.3.3 I/O port control registers AFRL[31:0] Each of the GPIOs has four 32-bit memory-mapped control registers (GPIOx_MODER, GPIOx_OTYPER, GPIOx_OSPEEDR, GPIOx_PUPDR) to configure up to 16 I/Os. The GPIOx_MODER register is used to select the I/O direction (input, output, AF, analog). The 191/1416 Doc ID 018909 Rev 3 Pin x (x = 0..7) For pins 8 to 15, the GPIOx_AFRH[31:0] register selects the dedicated alternate function AF0 (system) AF1 (TIM1/TIM2) AF2 (TIM3..5) AF3 (TIM8..11) AF4 (I2C1..3) AF5 (SPI1/2/4/5/6) AF6 (SPI3) AF7 (USART1..3) AF8 (USART4..8) AF9 (CAN1/CAN2, TIM12..14) AF10 (OTG_FS, OTG_HS) AF11 (ETH) AF12 (FSMC, SDIO, OTG_HS (1) ) AF13 (DCMI) AF14 AF15 (EVENTOUT) 1 AFRH[31:0] Pin x (x = 8..15) 1 MS30435V1
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RM0090 Reference manual STM32F40x,
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Contents RM0090 3.5.3 Erase . . . .
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Contents RM0090 6.3.1 RCC clock con
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Contents RM0090 7.4.7 GPIO port bit
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Contents RM0090 10.3.4 Falling trig
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Contents RM0090 12.4.2 Independent
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Contents RM0090 14.3.3 Repetition c
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Contents RM0090 15.4.12 TIMx auto-r
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Contents RM0090 17.4.6 TIM6&TIM7 co
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Contents RM0090 22.1 HASH introduct
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Contents RM0090 24.3.3 Tx mailboxes
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Contents RM0090 26.3.14 Hardware fl
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Contents RM0090 28.4.13 SD I/O mode
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Contents RM0090 29.7 Ethernet inter
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Contents RM0090 31.3.1 High-speed O
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Contents RM0090 33.2 Reference ARM
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List of tables RM0090 List of table
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List of tables RM0090 Table 98. Tra
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List of tables RM0090 Table 192. NO
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List of figures RM0090 Figure 49. A
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List of figures RM0090 Figure 151.
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Documentation conventions RM0090 1
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Memory and bus architecture RM0090
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Embedded Flash memory interface RM0
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CRC calculation unit RM0090 4 CRC c
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CRC calculation unit RM0090 Bits 7:
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Power control (PWR) RM0090 Figure 7
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Power control (PWR) RM0090 When the
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Power control (PWR) RM0090 mode (se
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Power control (PWR) RM0090 A PVDO f
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Power control (PWR) RM0090 5.3.3 Sl
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Power control (PWR) RM0090 If an ac
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Power control (PWR) RM0090 I/O stat
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Power control (PWR) RM0090 Safe RTC
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Power control (PWR) RM0090 Bit 4 PV
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Power control (PWR) RM0090 5.4.3 PW
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Reset and clock control for (RCC) R
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DMA controller (DMA) RM0090 15 14 1
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DMA controller (DMA) RM0090 9.5.11
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DMA controller (DMA) RM0090 Table 4
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Interrupts and events RM0090 10 Int
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Interrupts and events RM0090 Table
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Interrupts and events RM0090 genera
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Interrupts and events RM0090 10.3 E
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Interrupts and events RM0090 15 14
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Analog-to-digital converter (ADC) R
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Basic timers (TIM6&TIM7) RM0090 17
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Basic timers (TIM6&TIM7) RM0090 Fig
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Basic timers (TIM6&TIM7) RM0090 17.
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Independent watchdog (IWDG) RM0090
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Independent watchdog (IWDG) RM0090
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Window watchdog (WWDG) RM0090 19 Wi
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Window watchdog (WWDG) RM0090 case,
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Window watchdog (WWDG) RM0090 19.6
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Window watchdog (WWDG) RM0090 19.6.
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Hash processor (HASH) RM0090 22.3 H
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Hash processor (HASH) RM0090 has le
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Hash processor (HASH) RM0090 The le
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Hash processor (HASH) RM0090 with v
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Hash processor (HASH) RM0090 Proced
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Hash processor (HASH) RM0090 Bit 12
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Hash processor (HASH) RM0090 22.4.2
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Hash processor (HASH) RM0090 Bit 3
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Hash processor (HASH) RM0090 Table
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Real-time clock (RTC) RM0090 23.2 R
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Debug support (DBG) RM0090 33 Debug
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Debug support (DBG) RM0090 Only the
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Debug support (DBG) RM0090 Note: No
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Debug support (DBG) RM0090 31 30 29
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Debug support (DBG) RM0090 Bit 20:1
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Device electronic signature RM0090
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A ADC_CCR . . . . . . . . . . . . .
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DMA_SxM1AR . . . . . . . . . . . .
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HASH_SR . . . . . . . . . . . . . .
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RNG_DR . . . . . . . . . . . . . .
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Revision history RM0090 Revision hi
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Revision history RM0090 Table 238.
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