RM0090: Reference manual - STMicroelectronics

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<strong>RM0090</strong> General-purpose timers (TIM9 to TIM14) 16.5.12 TIM9/12 capture/compare register 1 (TIMx_CCR1) Address offset: 0x34 Reset value: 0x0000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CCR1[15:0] rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw Bits 15:0 CCR1[15:0]: Capture/Compare 1 value If channel CC1 is configured as output: CCR1 is the value to be loaded into the actual capture/compare 1 register (preload value). It is loaded permanently if the preload feature is not selected in the TIMx_CCMR1 register (OC1PE bit). Else the preload value is copied into the active capture/compare 1 register when an update event occurs. The active capture/compare register contains the value to be compared to the TIMx_CNT counter and signaled on the OC1 output. If channel CC1is configured as input: CCR1 is the counter value transferred by the last input capture 1 event (IC1). 16.5.13 TIM9/12 capture/compare register 2 (TIMx_CCR2) Address offset: 0x38 Reset value: 0x0000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 16.5.14 TIM9/12 register map CCR2[15:0] rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw Bits 15:0 CCR2[15:0]: Capture/Compare 2 value If channel CC2 is configured as output: CCR2 is the value to be loaded into the actual capture/compare 2 register (preload value). It is loaded permanently if the preload feature is not selected in the TIMx_CCMR2 register (OC2PE bit). Else the preload value is copied into the active capture/compare 2 register when an update event occurs. The active capture/compare register contains the value to be compared to the TIMx_CNT counter and signalled on the OC2 output. If channel CC2 is configured as input: CCR2 is the counter value transferred by the last input capture 2 event (IC2). TIM9/12 registers are mapped as 16-bit addressable registers as described below: 31 Table 79. TIM9/12 register map and reset values Offset Register 0x00 0x04 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 OPM TIMx_CR1 Reserved CKD [1:0] Reserved Reset value 0 0 0 0 0 0 0 TIMx_CR2 Reserved MMS[2:0] Reset value 0 0 0 Doc ID 018909 Rev 3 510/1416 ARPE URS UDIS Reserved CEN
General-purpose timers (TIM9 to TIM14) <strong>RM0090</strong> 31 Table 79. TIM9/12 register map and reset values (continued) Offset Register 0x08 0x0C 0x10 TIMx_SMCR Refer to Table 2 on page 53 for the register boundary addresses. 511/1416 Doc ID 018909 Rev 3 Reserved MSM TS[2:0] Reserved SMS[2:0] Reset value 0 0 0 0 0 0 0 CC2IE CC1IE UIE TIE TIMx_DIER Reserved Reserved Reset value 0 0 0 0 TIMx_SR Reserved Reserved Reset value 0 0 0 0 0 0 OC2PE OC2FE CC2OF CC1OF Reserved Reserved TIF CC2IF CC1IF UIF CC2G CC1G UG TG 0x14 TIMx_EGR Reserved Reserved Reset value 0 0 0 0 TIMx_CCMR1 Output Compare mode Reserved OC2M [2:0] CC2S [1:0] OC1M [2:0] CC1S [1:0] 0x18 Reset value TIMx_CCMR1 Input Capture mode Reserved 0 0 0 IC2F[3:0] 0 0 IC2 PSC [1:0] 0 0 CC2S [1:0] 0 0 0 IC1F[3:0] 0 0 IC1 PSC [1:0] 0 0 CC1S [1:0] Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x1C Reserved 0x20 0x24 0x28 0x2C TIMx_CCER Reserved Reset value 0 0 0 0 0 0 TIMx_CNT Reserved CNT[15:0] Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TIMx_PSC Reserved PSC[15:0] Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TIMx_ARR Reserved ARR[15:0] Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x30 Reserved 0x34 0x38 0x3C to 0x4C 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TIMx_CCR1 Reserved CCR1[15:0] Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TIMx_CCR2 Reserved CCR2[15:0] Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reserved CC2NP Reserved CC2P CC2E CC1NP OC1PE OC1FE Reserved CC1P CC1E
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RM0090 Reference manual STM32F40x,
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Contents RM0090 3.5.3 Erase . . . .
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Contents RM0090 6.3.1 RCC clock con
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Contents RM0090 7.4.7 GPIO port bit
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Contents RM0090 10.3.4 Falling trig
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Contents RM0090 12.4.2 Independent
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Contents RM0090 14.3.3 Repetition c
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Contents RM0090 15.4.12 TIMx auto-r
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Contents RM0090 17.4.6 TIM6&TIM7 co
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Contents RM0090 22.1 HASH introduct
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Contents RM0090 24.3.3 Tx mailboxes
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Contents RM0090 26.3.14 Hardware fl
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Contents RM0090 28.4.13 SD I/O mode
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Contents RM0090 29.7 Ethernet inter
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Contents RM0090 31.3.1 High-speed O
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Contents RM0090 33.2 Reference ARM
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List of tables RM0090 List of table
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List of tables RM0090 Table 98. Tra
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List of tables RM0090 Table 192. NO
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List of figures RM0090 Figure 49. A
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List of figures RM0090 Figure 151.
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Documentation conventions RM0090 1
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Memory and bus architecture RM0090
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Embedded Flash memory interface RM0
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CRC calculation unit RM0090 4 CRC c
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CRC calculation unit RM0090 Bits 7:
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Power control (PWR) RM0090 Figure 7
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Power control (PWR) RM0090 When the
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Power control (PWR) RM0090 mode (se
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Power control (PWR) RM0090 A PVDO f
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Power control (PWR) RM0090 5.3.3 Sl
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Power control (PWR) RM0090 If an ac
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Power control (PWR) RM0090 I/O stat
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Power control (PWR) RM0090 Safe RTC
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Power control (PWR) RM0090 Bit 4 PV
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Power control (PWR) RM0090 5.4.3 PW
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DMA controller (DMA) RM0090 9 DMA c
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DMA controller (DMA) RM0090 9.3 DMA
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DMA controller (DMA) RM0090 Figure
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DMA controller (DMA) RM0090 Table 3
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DMA controller (DMA) RM0090 In dire
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DMA controller (DMA) RM0090 Figure
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DMA controller (DMA) RM0090 memory
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DMA controller (DMA) RM0090 9.3.11
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DMA controller (DMA) RM0090 9.4 DMA
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DMA controller (DMA) RM0090 9.5.5 D
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DMA controller (DMA) RM0090 15 14 1
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Interrupts and events RM0090 Table
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Hash processor (HASH) RM0090 22.3 H
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Hash processor (HASH) RM0090 has le
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Hash processor (HASH) RM0090 with v
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Hash processor (HASH) RM0090 Proced
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Hash processor (HASH) RM0090 Bit 12
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Hash processor (HASH) RM0090 22.4.2
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Hash processor (HASH) RM0090 Bit 3
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Debug support (DBG) RM0090 33 Debug
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Device electronic signature RM0090
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A ADC_CCR . . . . . . . . . . . . .
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HASH_SR . . . . . . . . . . . . . .
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RNG_DR . . . . . . . . . . . . . .
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Revision history RM0090 Revision hi
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Revision history RM0090 Table 238.
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RM0090: Reference manual - STMicroelectronics

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