RM0090: Reference manual - STMicroelectronics

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<strong>RM0090</strong> Embedded Flash memory interface Bits 3:2 BOR_LEV: BOR reset Level These bits contain the supply level threshold that activates/releases the reset. They can be written to program a new BOR level. By default, BOR is off. When the supply voltage (V DD) drops below the selected BOR level, a device reset is generated. 00: BOR Level 3 (VBOR3), reset threshold level for 2.70 to 3.60 V voltage range 01: BOR Level 2 (VBOR2), reset threshold level for 2.40 to 2.70 V voltage range 10: BOR Level 1 (VBOR1), reset threshold level for 2.10 to 2.40 V voltage range 11: BOR off (VBOR0), reset threshold level for 1.80 to 2.10 V voltage range Note: For full details about BOR characteristics, refer to the "Electrical characteristics" section in the device datasheet. Bit 1 OPTSTRT: Option start This bit triggers a user option operation when set. It is set only by software and cleared when the BSY bit is cleared. Bit 0 OPTLOCK: Option lock Write to 1 only. When this bit is set, it indicates that the FLASH_OPTCR register is locked. This bit is cleared by hardware after detecting the unlock sequence. In the event of an unsuccessful unlock operation, this bit remains set until the next reset. 3.8.8 Flash option control register (FLASH_OPTCR1) for STM32F42x and STM32F43x This register is available only on STM32F42x and STM32F43x. The FLASH_OPTCR1 register is used to modify the user option bytes for sectors 12 to 23. Address offset: 0x18 Reset value: 0x0FFF 0000. The option bits are loaded with values from Flash memory at reset release. Access: no wait state when no Flash memory operation is ongoing, word, half-word and byte access. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved nWRP[11:0] rw rw rw rw rw rw rw rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bits 31:28 Reserved, must be kept cleared. Reserved Bits 27:16 nWRP: Not write protect These bits contain the value of the write-protection option bytes for sectors 12 to 23 after reset. They can be written to program a new write protect value into Flash memory. 0: Write protection active 1: Write protection not active Bits 15:0 Reserved, must be kept cleared. Doc ID 018909 Rev 3 84/1416
Embedded Flash memory interface <strong>RM0090</strong> 3.8.9 Flash interface register map Table 15. Flash register map and reset values (STM32F40x and STM32F41x) Offset Register 31 0x00 0x04 0x08 0x0C 0x10 0x14 FLASH_ACR 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved 85/1416 Doc ID 018909 Rev 3 DCRST ICRST DCEN ICEN PRFTEN Reserved LATENCY Reset value 0 0 0 0 0 0 0 0 FLASH_KEY R KEY[31:16] KEY[15:0] Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FLASH_OPT KEYR OPTKEYR[31:16] OPTKEYR[15:0] Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FLASH_SR Reserved BSY Reserved PGSERR PGPERR PGAERR WRPERR Reset value 0 0 0 0 0 0 0 STRT FLASH_CR Reserved Reserved Reserved PSIZ E[1:0 ] SNB[3:0] Reset value 1 0 0 0 0 0 0 0 0 0 0 LOCK FLASH_OPT CR Reserved EOPIE nWRP[11:0] RDP[7:0] Reserved nRST_STDBY nRST_STOP WDG_SW Reserved Reset value 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 0 1 0 1 0 1 1 1 1 1 0 1 31 Table 16. Flash register map and reset values (STM32F42x and STM32F43x) Offset Register 0x00 0x04 0x08 0x0C 0x10 FLASH_ACR 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved DCRST ICRST DCEN ICEN PRFTEN Reserved Reserved BOR_LEV MER OPERR SER OPTSTRT EOP PG OPTLOCK LATENCY Reset value 0 0 0 0 0 0 0 0 FLASH_KEYR KEY[31:16] KEY[15:0] Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FLASH_OPTKE YR OPTKEYR[31:16] OPTKEYR[15:0] Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FLASH_SR Reserved BSY Reserved PGSERR PGPERR PGAERR WRPERR Reset value 0 0 0 0 0 0 0 FLASH_CR LOCK Reserved EOPIE Reserved STRT MER1 Reserved PSIZE[1:0] SNB[4:0] Reset value 1 0 0 0 0 0 0 0 0 0 0 0 0 0 Reserved MER OPERR SER EOP PG
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RM0090 Reference manual STM32F40x,
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Contents RM0090 3.5.3 Erase . . . .
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Contents RM0090 6.3.1 RCC clock con
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Contents RM0090 7.4.7 GPIO port bit
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Contents RM0090 10.3.4 Falling trig
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Contents RM0090 12.4.2 Independent
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Contents RM0090 14.3.3 Repetition c
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Contents RM0090 15.4.12 TIMx auto-r
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Contents RM0090 17.4.6 TIM6&TIM7 co
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Contents RM0090 22.1 HASH introduct
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Contents RM0090 24.3.3 Tx mailboxes
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Contents RM0090 26.3.14 Hardware fl
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Contents RM0090 28.4.13 SD I/O mode
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Contents RM0090 29.7 Ethernet inter
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Contents RM0090 31.3.1 High-speed O
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Contents RM0090 33.2 Reference ARM
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Page 49 and 50: Memory and bus architecture RM0090
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DMA controller (DMA) RM0090 9 DMA c
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DMA controller (DMA) RM0090 9.3 DMA
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DMA controller (DMA) RM0090 Figure
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DMA controller (DMA) RM0090 Table 3
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DMA controller (DMA) RM0090 In dire
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DMA controller (DMA) RM0090 memory
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DMA controller (DMA) RM0090 9.3.11
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DMA controller (DMA) RM0090 9.4 DMA
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Interrupts and events RM0090 Table
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Interrupts and events RM0090 genera
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Independent watchdog (IWDG) RM0090
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Independent watchdog (IWDG) RM0090
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Window watchdog (WWDG) RM0090 19 Wi
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Window watchdog (WWDG) RM0090 case,
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Window watchdog (WWDG) RM0090 19.6
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Window watchdog (WWDG) RM0090 19.6.
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Hash processor (HASH) RM0090 with v
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Hash processor (HASH) RM0090 Proced
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Hash processor (HASH) RM0090 Bit 12
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Hash processor (HASH) RM0090 22.4.2
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Hash processor (HASH) RM0090 Bit 3
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Hash processor (HASH) RM0090 Table
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Real-time clock (RTC) RM0090 23.2 R
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Debug support (DBG) RM0090 33 Debug
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Device electronic signature RM0090
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A ADC_CCR . . . . . . . . . . . . .
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DMA_SxM1AR . . . . . . . . . . . .
Page 1405 and 1406:
HASH_SR . . . . . . . . . . . . . .
Page 1407 and 1408:
RNG_DR . . . . . . . . . . . . . .
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Revision history RM0090 Revision hi
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Revision history RM0090 Table 238.
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Page 1415 and 1416:
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RM0090: Reference manual - STMicroelectronics

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