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RM0090: Reference manual - STMicroelectronics

RM0090: Reference manual - STMicroelectronics

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<strong>RM0090</strong> USB on-the-go high-speed (OTG_HS)<br />

OTG_HS device control register (OTG_HS_DCTL)<br />

Address offset: 0x804<br />

Reset value: 0x0000 0000<br />

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0<br />

Reserved<br />

Bits 31:12 Reserved, must be kept at reset value.<br />

POPRGDNE<br />

CGONAK<br />

SGONAK<br />

Doc ID 018909 Rev 3 1218/1416<br />

CGINAK<br />

SGINAK<br />

TCTL<br />

GONSTS<br />

GINSTS<br />

SDIS<br />

RWUSIG<br />

rw w w w w rw rw rw r r rw rw<br />

Bit 11 POPRGDNE: Power-on programming done<br />

The application uses this bit to indicate that register programming is completed after a<br />

wakeup from power down mode.<br />

Bit 10 CGONAK: Clear global OUT NAK<br />

A write to this field clears the Global OUT NAK.<br />

Bit 9 SGONAK: Set global OUT NAK<br />

A write to this field sets the Global OUT NAK.<br />

The application uses this bit to send a NAK handshake on all OUT endpoints.<br />

The application must set the this bit only after making sure that the Global OUT NAK<br />

effective bit in the Core interrupt register (GONAKEFF bit in OTG_HS_GINTSTS) is cleared.<br />

Bit 8 CGINAK: Clear global IN NAK<br />

A write to this field clears the Global IN NAK.<br />

Bit 7 SGINAK: Set global IN NAK<br />

A write to this field sets the Global nonperiodic IN NAK.The application uses this bit to send<br />

a NAK handshake on all nonperiodic IN endpoints.<br />

The application must set this bit only after making sure that the Global IN NAK effective bit<br />

in the Core interrupt register (GINAKEFF bit in OTG_HS_GINTSTS) is cleared.<br />

Bits 6:4 TCTL: Test control<br />

000: Test mode disabled<br />

001: Test_J mode<br />

010: Test_K mode<br />

011: Test_SE0_NAK mode<br />

100: Test_Packet mode<br />

101: Test_Force_Enable<br />

Others: Reserved<br />

Bit 3 GONSTS: Global OUT NAK status<br />

0: A handshake is sent based on the FIFO Status and the NAK and STALL bit settings.<br />

1: No data is written to the RxFIFO, irrespective of space availability. Sends a NAK<br />

handshake on all packets, except on SETUP transactions. All isochronous OUT packets are<br />

dropped.

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