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RM0090: Reference manual - STMicroelectronics

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Inter-integrated circuit (I 2 C) interface <strong>RM0090</strong><br />

25.6.5 I 2 C Data register (I2C_DR)<br />

Address offset: 0x10<br />

Reset value: 0x0000<br />

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0<br />

Reserved<br />

Bits 15:8 Reserved, must be kept at reset value<br />

25.6.6 I 2 C Status register 1 (I2C_SR1)<br />

Address offset: 0x14<br />

Reset value: 0x0000<br />

729/1416 Doc ID 018909 Rev 3<br />

DR[7:0]<br />

rw rw rw rw rw rw rw rw<br />

Bits 7:0 DR[7:0] 8-bit data register<br />

Byte received or to be transmitted to the bus.<br />

–Transmitter mode: Byte transmission starts automatically when a byte is written in the DR<br />

register. A continuous transmit stream can be maintained if the next data to be transmitted<br />

is put in DR once the transmission is started (TxE=1)<br />

–Receiver mode: Received byte is copied into DR (RxNE=1). A continuous transmit stream<br />

can be maintained if DR is read before the next data byte is received (RxNE=1).<br />

Note: In slave mode, the address is not copied into DR.<br />

Note: Write collision is not managed (DR can be written if TxE=0).<br />

Note: If an ARLO event occurs on ACK pulse, the received byte is not copied into DR and so<br />

cannot be read.<br />

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0<br />

SMB<br />

ALERT<br />

TIME<br />

OUT Res.<br />

PEC<br />

ERR<br />

OVR AF ARLO BERR TxE RxNE<br />

Res.<br />

STOPF ADD10 BTF ADDR SB<br />

rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 r r r r r r r<br />

Bit 15 SMBALERT: SMBus alert<br />

In SMBus host mode:<br />

0: no SMBALERT<br />

1: SMBALERT event occurred on pin<br />

In SMBus slave mode:<br />

0: no SMBALERT response address header<br />

1: SMBALERT response address header to SMBALERT LOW received<br />

– Cleared by software writing 0, or by hardware when PE=0.<br />

Bit 14 TIMEOUT: Timeout or Tlow error<br />

0: No timeout error<br />

1: SCL remained LOW for 25 ms (Timeout)<br />

or<br />

Master cumulative clock low extend time more than 10 ms (Tlow:mext)<br />

or<br />

Slave cumulative clock low extend time more than 25 ms (Tlow:sext)<br />

– When set in slave mode: slave resets the communication and lines are released by hardware<br />

– When set in master mode: Stop condition sent by hardware<br />

– Cleared by software writing 0, or by hardware when PE=0.<br />

Note: This functionality is available only in SMBus mode.

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