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RM0090: Reference manual - STMicroelectronics

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<strong>RM0090</strong> Controller area network (bxCAN)<br />

Figure 224. Dual CAN block diagram<br />

Control/Status/Configuration<br />

Control/Status/Configuration<br />

Master Control<br />

Master Status<br />

Tx Status<br />

Rx FIFO 0 St at us<br />

Rx FIFO 1 St at us<br />

Interrupt Enable<br />

Error Status<br />

Bit Timing<br />

Filter Master<br />

Filter Mode<br />

Filter Scale<br />

Filter FIFO Assign<br />

Filter Activation<br />

Master Control<br />

Master Status<br />

Tx Status<br />

Rx FIFO 0 St at us<br />

Rx FIFO 1 St at us<br />

Interrupt Enable<br />

Error Status<br />

Bit Timing<br />

CAN2 (Slave)<br />

CAN 2.0B Active Core<br />

CAN 2.0B Active Core<br />

24.4 bxCAN operating modes<br />

CAN1 (Master) with 512 bytes SRAM<br />

Master<br />

Tx Mailboxes<br />

2<br />

1<br />

Mailbox 0<br />

Transmission<br />

Scheduler<br />

Memory<br />

Access<br />

Controller<br />

Transmission<br />

Scheduler<br />

Slave<br />

Tx Mailboxes<br />

2<br />

1<br />

Mailbox 0<br />

Acceptance Filters<br />

bxCAN has three main operating modes: initialization, normal and Sleep. After a<br />

hardware reset, bxCAN is in Sleep mode to reduce power consumption and an internal pullup<br />

is active on CANTX. The software requests bxCAN to enter initialization or Sleep mode<br />

by setting the INRQ or SLEEP bits in the CAN_MCR register. Once the mode has been<br />

entered, bxCAN confirms it by setting the INAK or SLAK bits in the CAN_MSR register and<br />

the internal pull-up is disabled. When neither INAK nor SLAK are set, bxCAN is in normal<br />

Filter<br />

Master<br />

Receive FIFO 0<br />

2<br />

1<br />

Mailbox 0<br />

..<br />

26<br />

Doc ID 018909 Rev 3 662/1416<br />

0<br />

1<br />

Master Filters<br />

(0 to 27)<br />

2<br />

3<br />

Master<br />

Receive FIFO 1<br />

2<br />

1<br />

Mailbox 0<br />

Slave<br />

Receive FIFO 0<br />

Slave<br />

Receive FIFO 1<br />

2<br />

2<br />

Mailbox 0<br />

1<br />

Mailbox 0<br />

1<br />

..<br />

Slave Filters<br />

(0 to 27)<br />

Note: CAN 2 start filter bank number n is confi gurable by writing to<br />

the CAN2SB[5:0] bits in the CAN_ FMR register.<br />

27<br />

ai16094b

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