RM0090: Reference manual - STMicroelectronics

Analog-to-digital converter (ADC) RM0090
Note: Injected channels cannot be converted continuously. The only exception is when an injected
channel is configured to be converted automatically after regular channels in continuous
mode (using JAUTO bit), refer to Auto-injection section).
11.3.6 Timing diagram
As shown in Figure 35, the ADC needs a stabilization time of t STAB before it starts
converting accurately. After the start of the ADC conversion and after 15 clock cycles, the
EOC flag is set and the 16-bit ADC data register contains the result of the conversion.
Figure 35. Timing diagram
ADC_CLK
ADON
SWSTART/
JSWSTART
ADC
EOC
tSTAB
11.3.7 Analog watchdog
Start 1st conversion Start next conversion
ADC conversion
Conversion time
(total conv. time)
The AWD analog watchdog status bit is set if the analog voltage converted by the ADC is
below a lower threshold or above a higher threshold. These thresholds are programmed in
the 12 least significant bits of the ADC_HTR and ADC_LTR 16-bit registers. An interrupt can
be enabled by using the AWDIE bit in the ADC_CR1 register.
The threshold value is independent of the alignment selected by the ALIGN bit in the
ADC_CR2 register. The analog voltage is compared to the lower and higher thresholds
before alignment.
Table 47 shows how the ADC_CR1 register should be configured to enable the analog
watchdog on one or more channels.
Figure 36. Analog watchdog’s guarded area
Analog voltage
Higher threshold
Lower threshold
267/1416 Doc ID 018909 Rev 3
Software clears the EOC bit
Guarde d area
HTR
LT R
Next ADC conversion
ai16048
ai16047b