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RM0090: Reference manual - STMicroelectronics

RM0090: Reference manual - STMicroelectronics

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<strong>RM0090</strong> Digital camera interface (DCMI)<br />

13.8.3 DCMI raw interrupt status register (DCMI_RIS)<br />

Address offset: 0x08<br />

Reset value: 0x0000 0x0000<br />

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0<br />

Reserved<br />

DCMI_RIS gives the raw interrupt status and is accessible in read only. When read, this<br />

register returns the status of the corresponding interrupt before masking with the DCMI_IER<br />

register value.<br />

Bit 31:5 Reserved, must be kept at reset value.<br />

Doc ID 018909 Rev 3 340/1416<br />

LINE_RIS<br />

VSYNC_RIS<br />

ERR_RIS<br />

OVR_RIS<br />

FRAME_RIS<br />

r r r r r<br />

Bit 4 LINE_RIS: Line raw interrupt status<br />

This bit gets set when the HSYNC signal changes from the inactive state to the<br />

active state. It goes high even if the line is not valid.<br />

In the case of embedded synchronization, this bit is set only if the CAPTURE bit<br />

in DCMI_CR is set.<br />

It is cleared by writing a ‘1’ to the LINE_ISC bit in DCMI_ICR.<br />

Bit 3 VSYNC_RIS: VSYNC raw interrupt status<br />

This bit is set when the VSYNC signal changes from the inactive state to the<br />

active state.<br />

In the case of embedded synchronization, this bit is set only if the CAPTURE bit<br />

is set in DCMI_CR.<br />

It is cleared by writing a ‘1’ to the VSYNC_ISC bit in DCMI_ICR.<br />

Bit 2 ERR_RIS: Synchronization error raw interrupt status<br />

0: No synchronization error detected<br />

1: Embedded synchronization characters are not received in the correct order.<br />

This bit is valid only in the embedded synchronization mode. It is cleared by<br />

writing a ‘1’ to the ERR_ISC bit in DCMI_ICR.<br />

Note: This bit is available only in embedded synchronization mode.<br />

Bit 1 OVR_RIS: Overrun raw interrupt status<br />

0: No data buffer overrun occurred<br />

1: A data buffer overrun occurred and the data FIFO is corrupted.<br />

This bit is cleared by writing a ‘1’ to the OVR_ISC bit in DCMI_ICR.<br />

Bit 0 FRAME_RIS: Capture complete raw interrupt status<br />

0: No new capture<br />

1: A frame has been captured.<br />

This bit is set when a frame or window has been captured.<br />

In case of a cropped window, this bit is set at the end of line of the last line in the<br />

crop. It is set even if the captured frame is empty (e.g. window cropped outside<br />

the frame).<br />

This bit is cleared by writing a ‘1’ to the FRAME_ISC bit in DCMI_ICR.

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