RM0090: Reference manual - STMicroelectronics

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<strong>RM0090</strong> Interrupts and events 10.2.5 External interrupt/event line mapping Up to 140 GPIOs (STM32F40x and STM32F41x) are connected to the 16 external interrupt/event lines in the following manner: Figure 33. External interrupt/event GPIO mapping EXTI0[3:0] bits in the SYSCFG_EXTICR1 register PA0 PB0 PC0 PD0 PE0 PF0 PG0 PH0 PI0 PA1 PB1 PC1 PD1 PE1 PF1 PG1 PH1 PI1 PA15 PB15 PC15 PD15 PE15 PF15 PG15 PH15 The seven other EXTI lines are connected as follows: ● EXTI line 16 is connected to the PVD output EXTI0 EXTI1[3:0] bits in the SYSCFG_EXTICR1 register EXTI1 EXTI15[3:0] bits in the SYSCFG_EXTICR4 register EXTI15 ● EXTI line 17 is connected to the RTC Alarm event ● EXTI line 18 is connected to the USB OTG FS Wakeup event ● EXTI line 19 is connected to the Ethernet Wakeup event ● EXTI line 20 is connected to the USB OTG HS (configured in FS) Wakeup event ● EXTI line 21 is connected to the RTC Tamper and TimeStamp events ● EXTI line 22 is connected to the RTC Wakeup event . . . ai15897 Doc ID 018909 Rev 3 258/1416
Interrupts and events <strong>RM0090</strong> 10.3 EXTI registers Refer to Section 1.1 on page 47 for a list of abbreviations used in register descriptions. 10.3.1 Interrupt mask register (EXTI_IMR) Address offset: 0x00 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 10.3.2 Event mask register (EXTI_EMR) Address offset: 0x04 Reset value: 0x0000 0000 10.3.3 Rising trigger selection register (EXTI_RTSR) Address offset: 0x08 Reset value: 0x0000 0000 259/1416 Doc ID 018909 Rev 3 MR22 MR21 MR20 MR19 MR18 MR17 MR16 rw rw rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 MR15 MR14 MR13 MR12 MR11 MR10 MR9 MR8 MR7 MR6 MR5 MR4 MR3 MR2 MR1 MR0 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw Bits 31:23 Reserved, must be kept at reset value. Bits 22:0 MRx: Interrupt mask on line x 0: Interrupt request from line x is masked 1: Interrupt request from line x is not masked 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved MR22 MR21 MR20 MR19 MR18 MR17 MR16 rw rw rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 MR15 MR14 MR13 MR12 MR11 MR10 MR9 MR8 MR7 MR6 MR5 MR4 MR3 MR2 MR1 MR0 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw Bits 31:23 Reserved, must be kept at reset value. Bits 22:0 MRx: Event mask on line x 0: Event request from line x is masked 1: Event request from line x is not masked 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved TR22 TR21 TR20 TR19 TR18 TR17 TR16 rw rw rw rw rw rw rw
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RM0090 Reference manual STM32F40x,
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Contents RM0090 3.5.3 Erase . . . .
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Contents RM0090 6.3.1 RCC clock con
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Contents RM0090 31.3.1 High-speed O
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Contents RM0090 33.2 Reference ARM
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List of tables RM0090 List of table
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List of tables RM0090 Table 98. Tra
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List of tables RM0090 Table 192. NO
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Documentation conventions RM0090 1
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Memory and bus architecture RM0090
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Power control (PWR) RM0090 Figure 7
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Power control (PWR) RM0090 When the
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Power control (PWR) RM0090 mode (se
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Power control (PWR) RM0090 A PVDO f
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Power control (PWR) RM0090 5.3.3 Sl
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Power control (PWR) RM0090 If an ac
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Power control (PWR) RM0090 I/O stat
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Power control (PWR) RM0090 Safe RTC
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Hash processor (HASH) RM0090 Proced
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Hash processor (HASH) RM0090 Bit 12
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Hash processor (HASH) RM0090 22.4.2
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Hash processor (HASH) RM0090 Bit 3
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Debug support (DBG) RM0090 33 Debug
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Device electronic signature RM0090
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A ADC_CCR . . . . . . . . . . . . .
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DMA_SxM1AR . . . . . . . . . . . .
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HASH_SR . . . . . . . . . . . . . .
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RNG_DR . . . . . . . . . . . . . .
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Revision history RM0090 Revision hi
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Revision history RM0090 Table 238.
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