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RM0090: Reference manual - STMicroelectronics

RM0090: Reference manual - STMicroelectronics

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USB on-the-go full-speed (OTG_FS) <strong>RM0090</strong><br />

30.16.4 Device-mode registers<br />

OTG_FS device configuration register (OTG_FS_DCFG)<br />

Address offset: 0x800<br />

Reset value: 0x0220 0000<br />

This register configures the core in device mode after power-on or after certain control<br />

commands or enumeration. Do not make changes to this register after initial programming.<br />

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0<br />

Reserved PFIVL<br />

Bits 31:13 Reserved, must be kept at reset value.<br />

1079/1416 Doc ID 018909 Rev 3<br />

DAD<br />

Reserved<br />

NZLSOHSK<br />

DSPD<br />

rw rw rw rw rw rw rw rw rw rw rw<br />

Bits 12:11 PFIVL: Periodic frame interval<br />

Indicates the time within a frame at which the application must be notified using the end of<br />

periodic frame interrupt. This can be used to determine if all the isochronous traffic for that<br />

frame is complete.<br />

00: 80% of the frame interval<br />

01: 85% of the frame interval<br />

10: 90% of the frame interval<br />

11: 95% of the frame interval<br />

Bits 10:4 DAD: Device address<br />

The application must program this field after every SetAddress control command.<br />

Bit 3 Reserved, must be kept at reset value.<br />

Bit 2 NZLSOHSK: Non-zero-length status OUT handshake<br />

The application can use this field to select the handshake the core sends on receiving a<br />

nonzero-length data packet during the OUT transaction of a control transfer’s Status stage.<br />

1: Send a STALL handshake on a nonzero-length status OUT transaction and do not send<br />

the received OUT packet to the application.<br />

0: Send the received OUT packet to the application (zero-length or nonzero-length) and<br />

send a handshake based on the NAK and STALL bits for the endpoint in the Device endpoint<br />

control register.<br />

Bits 1:0 DSPD: Device speed<br />

Indicates the speed at which the application requires the core to enumerate, or the<br />

maximum speed the application can support. However, the actual bus speed is determined<br />

only after the chirp sequence is completed, and is based on the speed of the USB host to<br />

which the core is connected.<br />

00: Reserved<br />

01: Reserved<br />

10: Reserved<br />

11: Full speed (USB 1.1 transceiver clock is 48 MHz)

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