RM0090: Reference manual - STMicroelectronics

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<strong>RM0090</strong> Embedded Flash memory interface Bit 24 EOPIE: End of operation interrupt enable This bit enables the interrupt generation when the EOP bit in the FLASH_SR register goes to 1. 0: Interrupt generation disabled 1: Interrupt generation enabled Bits 23:17 Reserved, must be kept cleared. Bit 16 STRT: Start This bit triggers an erase operation when set. It is set only by software and cleared when the BSY bit is cleared. Bit 15 MER1: Mass Erase of sectors 12 to 23 Erase activated of user sectors 12 to 23. Bits 14:10 Reserved, must be kept cleared. Bits 9:8 PSIZE: Program size These bits select the program parallelism. 00 program x8 01 program x16 10 program x32 11 program x64 Bits 7:3 SNB: Sector number These bits select the sector to erase. 0000: sector 0 0001: sector 1 ... 01011: sector 11 01100: not allowed 01101: not allowed 01110: not allowed 01111: not allowed 10000: section 12 10001: section 13 ... 11011 sector 23 11100: not allowed 11101: not allowed 11110: not allowed 11111: not allowed Bit 2 MER: Mass Erase of sectors 0 to 11 Erase activated of user sectors 0 to 11. Bit 1 SER: Sector Erase Sector Erase activated. Bit 0 PG: Programming Flash programming activated. Doc ID 018909 Rev 3 82/1416
Embedded Flash memory interface <strong>RM0090</strong> 3.8.7 Flash option control register (FLASH_OPTCR) The FLASH_OPTCR register is used to modify the user option bytes. Address offset: 0x14 Reset value: 0x0FFF AAED. The option bits are loaded with values from Flash memory at reset release. Access: no wait state when no Flash memory operation is ongoing, word, half-word and byte access. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 83/1416 Doc ID 018909 Rev 3 nWRP[11:0] rw rw rw rw rw rw rw rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 nRST_ nRST_ WDG_ OPTST OPTLO RDP[7:0] STDBY STOP SW Reserv BOR_LEV RT CK ed rw rw rw rw rw rw rw rw rw rw rw rw rw rs rs Bits 31:28 Reserved, must be kept cleared. Bits 27:16 nWRP: Not write protect These bits contain the value of the write-protection option bytes of sectors after reset. They can be written to program a new write protect value into Flash memory. 0: Write protection active on selected sector 1: Write protection not active on selected sector Bits 15:8 RDP: Read protect These bits contain the value of the read-protection option level after reset. They can be written to program a new read protection value into Flash memory. 0xAA: Level 0, read protection not active 0xCC: Level 2, chip read protection active Others: Level 1, read protection of memories active Bits 7:5 USER: User option bytes These bits contain the value of the user option byte after reset. They can be written to program a new user option byte value into Flash memory. Bit 7: nRST_STDBY Bit 6: nRST_STOP Bit 5: WDG_SW Note: When changing the WDG mode from hardware to software or from software to hardware, a system reset is required to make the change effective. Bit 4 Reserved, must be kept cleared.
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RM0090 Reference manual STM32F40x,
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Contents RM0090 3.5.3 Erase . . . .
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Contents RM0090 6.3.1 RCC clock con
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Contents RM0090 7.4.7 GPIO port bit
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Contents RM0090 10.3.4 Falling trig
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Contents RM0090 12.4.2 Independent
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Contents RM0090 14.3.3 Repetition c
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Contents RM0090 15.4.12 TIMx auto-r
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Contents RM0090 17.4.6 TIM6&TIM7 co
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Contents RM0090 22.1 HASH introduct
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Contents RM0090 24.3.3 Tx mailboxes
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Contents RM0090 26.3.14 Hardware fl
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Contents RM0090 28.4.13 SD I/O mode
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Contents RM0090 29.7 Ethernet inter
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Contents RM0090 31.3.1 High-speed O
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Page 49 and 50: Memory and bus architecture RM0090
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Reset and clock control for (RCC) R
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DMA controller (DMA) RM0090 9 DMA c
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DMA controller (DMA) RM0090 9.3 DMA
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DMA controller (DMA) RM0090 Figure
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DMA controller (DMA) RM0090 Table 3
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DMA controller (DMA) RM0090 In dire
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DMA controller (DMA) RM0090 Figure
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DMA controller (DMA) RM0090 memory
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DMA controller (DMA) RM0090 9.3.11
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DMA controller (DMA) RM0090 9.4 DMA
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DMA controller (DMA) RM0090 Bits 25
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DMA controller (DMA) RM0090 9.5.5 D
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DMA controller (DMA) RM0090 Bits 8
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DMA controller (DMA) RM0090 15 14 1
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Interrupts and events RM0090 10 Int
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Interrupts and events RM0090 Table
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Interrupts and events RM0090 genera
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Interrupts and events RM0090 10.3 E
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Interrupts and events RM0090 15 14
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Analog-to-digital converter (ADC) R
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Basic timers (TIM6&TIM7) RM0090 17
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Basic timers (TIM6&TIM7) RM0090 Fig
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Basic timers (TIM6&TIM7) RM0090 Fig
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Basic timers (TIM6&TIM7) RM0090 17.
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Independent watchdog (IWDG) RM0090
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Independent watchdog (IWDG) RM0090
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Window watchdog (WWDG) RM0090 19 Wi
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Window watchdog (WWDG) RM0090 case,
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Window watchdog (WWDG) RM0090 19.6
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Window watchdog (WWDG) RM0090 19.6.
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Hash processor (HASH) RM0090 22.3 H
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Hash processor (HASH) RM0090 has le
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Hash processor (HASH) RM0090 The le
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Hash processor (HASH) RM0090 with v
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Hash processor (HASH) RM0090 Proced
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Hash processor (HASH) RM0090 Bit 12
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Hash processor (HASH) RM0090 22.4.2
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Hash processor (HASH) RM0090 Bit 3
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Hash processor (HASH) RM0090 HASH_H
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Hash processor (HASH) RM0090 Table
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Real-time clock (RTC) RM0090 23.2 R
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Real-time clock (RTC) RM0090 The as
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Real-time clock (RTC) RM0090 23.3.5
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Real-time clock (RTC) RM0090 RTC_TR
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Real-time clock (RTC) RM0090 window
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Real-time clock (RTC) RM0090 Bit 3
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Debug support (DBG) RM0090 33 Debug
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Debug support (DBG) RM0090 Figure 4
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Debug support (DBG) RM0090 33.4.3 I
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Debug support (DBG) RM0090 Only the
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Debug support (DBG) RM0090 Note: No
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Debug support (DBG) RM0090 31 30 29
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Debug support (DBG) RM0090 Bit 20:1
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Device electronic signature RM0090
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A ADC_CCR . . . . . . . . . . . . .
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DMA_SxM1AR . . . . . . . . . . . .
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HASH_SR . . . . . . . . . . . . . .
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RNG_DR . . . . . . . . . . . . . .
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Revision history RM0090 Revision hi
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Revision history RM0090 Table 238.
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