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RM0090: Reference manual - STMicroelectronics

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Ethernet (ETH): media access control (MAC) with DMA controller <strong>RM0090</strong><br />

There are two modes of operation for popping data towards the MAC core:<br />

● In Threshold mode, as soon as the number of bytes in the FIFO crosses the configured<br />

threshold level (or when the end-of-frame is written before the threshold is crossed),<br />

the data is ready to be popped out and forwarded to the MAC core. The threshold level<br />

is configured using the TTC bits of ETH_DMABMR.<br />

● In Store-and-forward mode, only after a complete frame is stored in the FIFO, the frame<br />

is popped towards the MAC core. If the Tx FIFO size is smaller than the Ethernet frame<br />

to be transmitted, then the frame is popped towards the MAC core when the Tx FIFO<br />

becomes almost full.<br />

The application can flush the Transmit FIFO of all contents by setting the FTF<br />

(ETH_DMAOMR register [20]) bit. This bit is self-clearing and initializes the FIFO pointers to<br />

the default state. If the FTF bit is set during a frame transfer to the MAC core, then transfer is<br />

stopped as the FIFO is considered to be empty. Hence an underflow event occurs at the<br />

MAC transmitter and the corresponding Status word is forwarded to the DMA.<br />

Automatic CRC and pad generation<br />

When the number of bytes received from the application falls below 60 (DA+SA+LT+Data),<br />

zeros are appended to the transmitting frame to make the data length exactly 46 bytes to<br />

meet the minimum data field requirement of IEEE 802.3. The MAC can be programmed not<br />

to append any padding. The cyclic redundancy check (CRC) for the frame check sequence<br />

(FCS) field is calculated and appended to the data being transmitted. When the MAC is<br />

programmed to not append the CRC value to the end of Ethernet frames, the computed<br />

CRC is not transmitted. An exception to this rule is that when the MAC is programmed to<br />

append pads for frames (DA+SA+LT+Data) less than 60 bytes, CRC will be appended at the<br />

end of the padded frames.<br />

The CRC generator calculates the 32-bit CRC for the FCS field of the Ethernet frame. The<br />

encoding is defined by the following polynomial.<br />

Gx ( ) x 32<br />

x 26<br />

x 23<br />

=<br />

+ + + + + + + + + + + + + x + 1<br />

Transmit protocol<br />

The MAC controls the operation of Ethernet frame transmission. It performs the following<br />

functions to meet the IEEE 802.3/802.3z specifications. It:<br />

● generates the preamble and SFD<br />

● generates the jam pattern in Half-duplex mode<br />

● controls the Jabber timeout<br />

● controls the flow for Half-duplex mode (back pressure)<br />

● generates the transmit frame status<br />

● contains time stamp snapshot logic in accordance with IEEE 1588<br />

When a new frame transmission is requested, the MAC sends out the preamble and SFD,<br />

followed by the data. The preamble is defined as 7 bytes of 0b10101010 pattern, and the<br />

SFD is defined as 1 byte of 0b10101011 pattern. The collision window is defined as 1 slot<br />

time (512 bit times for 10/100 Mbit/s Ethernet). The jam pattern generation is applicable only<br />

to Half-duplex mode, not to Full-duplex mode.<br />

In MII mode, if a collision occurs at any time from the beginning of the frame to the end of<br />

the CRC field, the MAC sends a 32-bit jam pattern of 0x5555 5555 on the MII to inform all<br />

915/1416 Doc ID 018909 Rev 3<br />

x 22<br />

x 16<br />

x 12<br />

x 11<br />

x 10<br />

x 8<br />

x 7<br />

x 5<br />

x 4<br />

x 2

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