RM0090: Reference manual - STMicroelectronics

RM0090 Real-time clock (RTC)
Figure 222. RTC block diagram
LSE (32.768 Hz)
HSE_RTC
(4 MHz max)
LSI
RTC_TAMP1
Smooth
calibration
RTC_CALR
RTCCLK
Asyn ch.
7-bit prescaler
(default = 128)
ck_apre
(default 256 Hz)
1. On STM32F4xx devices, the RTC_AF1 and RTC_AF2 alternate functions are connected to PC13 and PI8, respectively.
23.3 RTC functional description
23.3.1 Clock and prescalers
512 Hz
RTC_PRER RTC_PRER
WUCKSEL[1:0]
Prescaler
/ 2, 4, 8, 16
Coarse
Calibration
RTC_CALIBR
1 Hz
Synchronous
15-bit prescaler
RTC_WUTR
16-bit wakeup
auto-reload timer
Alarm A
(RTC_ALRMAR
RTC_ALRMASSR
ck spre registers)
(default 1 Hz)
(default = 256) Calendar
Shadow register
(RTC_SSR)
Shadow registers
(RTC_TR,
RTC_DR)
RTC_TAMP2
Time stamp
registe rs
RTC_CALIB
The RTC clock source (RTCCLK) is selected through the clock controller among the LSE
clock, the LSI oscillator clock, and the HSE clock. For more information on the RTC clock
source configuration, refer to Section 6: Reset and clock control for (RCC).
A programmable prescaler stage generates a 1 Hz clock which is used to update the
calendar. To minimize power consumption, the prescaler is split into 2 programmable
prescalers (see Figure 222: RTC block diagram):
● A 7-bit asynchronous prescaler configured through the PREDIV_A bits of the
RTC_PRER register.
● A 15-bit synchronous prescaler configured through the PREDIV_S bits of the
RTC_PRER register.
MS19902V3
Note: When both prescalers are used, it is recommended to configure the asynchronous prescaler
to a high value to minimize consumption.
RTC_TS
Alarm B
(RTC_ALRMBR
RTC_ALRMBSSR
registers)
Backup and
RTC tamper
control registers
=
=
ALRAF
RTC_ALARM
ALRBF
Doc ID 018909 Rev 3 622/1416
TSF
WUTF
TAMPE
TSE
Output
control
RTC_OUT
RTC_AF1
RTC_AF2