RM0090: Reference manual - STMicroelectronics

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RM0090 DMA controller (DMA) Table 42. DMA register map and reset values (continued) Offset Register 0x00B8 DMA_S7CR Reserved CHSEL[2:0] MBURST[1:0] PBURST[1:0] ACK CT Refer to Table 2 on page 53 for the register boundary addresses. DBM PL[1:0] PINCOS MSIZE[1:0] PSIZE[1:0] MINC PINC Doc ID 018909 Rev 3 246/1416 CIRC DIR[1:0] PFCTRL TCIE HTIE TEIE DMEIE EN Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x00BC DMA_S7NDTR Reset value Reserved 0 0 0 0 0 0 NDT[15:.] 0 0 0 0 0 0 0 0 0 0 0x00C0 DMA_S7PAR Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PA[31:0] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x00C4 DMA_S7M0AR Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 M0A[31:0] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x00C8 DMA_S7M1AR Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 M1A[31:0] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x00CC DMA_S7FCR 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved FEIE Reserved FS[2:0] Reset value 0 1 0 0 0 0 1 DMDIS FTH [1:0]
Interrupts and events RM0090 10 Interrupts and events This Section applies to the whole STM32F4xx family, unless otherwise specified. 10.1 Nested vectored interrupt controller (NVIC) 10.1.1 NVIC features The nested vector interrupt controller NVIC includes the following features: ● 82 maskable interrupt channels for STM32F40x and STM32F41x, and up to 86 maskable interrupt channels for STM32F42x and STM32F43x (not including the 16 interrupt lines of Cortex-M4F) ● 16 programmable priority levels (4 bits of interrupt priority are used) ● low-latency exception and interrupt handling ● power management control ● implementation of system control registers The NVIC and the processor core interface are closely coupled, which enables low latency interrupt processing and efficient processing of late arriving interrupts. All interrupts including the core exceptions are managed by the NVIC. For more information on exceptions and NVIC programming see Chapter 5: Exceptions & Chapter 8: Nested Vectored Interrupt Controller in the ARM Cortex-M4F Technical Reference Manual. 10.1.2 SysTick calibration value register The SysTick calibration value is fixed to 18750, which gives a reference time base of 1 ms with the SysTick clock set to 18.75 MHz (HCLK/8, with HCLK set to 150 MHz). 10.1.3 Interrupt and exception vectors See Table 43 and Table 44, for the vector table for the STM32F40x and STM32F41x and STM32F42x and STM32F43x devices. 10.2 External interrupt/event controller (EXTI) The external interrupt/event controller consists of up to 23 edge detectors for generating event/interrupt requests. Each input line can be independently configured to select the type (interrupt or event) and the corresponding trigger event (rising or falling or both). Each line can also masked independently. A pending register maintains the status line of the interrupt requests. 247/1416 Doc ID 018909 Rev 3
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RM0090 Reference manual STM32F40x,
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Contents RM0090 3.5.3 Erase . . . .
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Contents RM0090 6.3.1 RCC clock con
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Contents RM0090 33.2 Reference ARM
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List of tables RM0090 List of table
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List of tables RM0090 Table 98. Tra
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Documentation conventions RM0090 1
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Memory and bus architecture RM0090
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Hash processor (HASH) RM0090 Proced
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Hash processor (HASH) RM0090 Bit 12
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Debug support (DBG) RM0090 33 Debug
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Device electronic signature RM0090
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A ADC_CCR . . . . . . . . . . . . .
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DMA_SxM1AR . . . . . . . . . . . .
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HASH_SR . . . . . . . . . . . . . .
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RNG_DR . . . . . . . . . . . . . .
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Revision history RM0090 Revision hi
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Revision history RM0090 Table 238.
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