RM0090: Reference manual - STMicroelectronics

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<strong>RM0090</strong> Analog-to-digital converter (ADC) Table 53. ADC register map and reset values for each ADC Offset Register 31 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C 0x40 0x44 0x48 0x4C 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 OVR ADC_SR Reserved Reset value 0 0 0 0 0 0 ADC_CR1 Reserved OVRIE RES[1:0] AWDEN JAWDEN Reserved DISC NUM [2:0] JDISCEN DISCEN STRT JSTRT JEOC EOC AWD Doc ID 018909 Rev 3 304/1416 JAUTO AWD SGL SCAN JEOCIE AWDIE EOCIE AWDCH[4:0] Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADC_CR2 Re se rv ed SWSTART EXTEN[1:0] EXTSEL [3:0] Re se rv ed JSWSTART JEXTEN[1:0] JEXTSEL [3:0] Reserved ALIGN EOCS DDS DMA Reserved Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADC_SMPR1 Sample time bits SMPx_x Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADC_SMPR2 Sample time bits SMPx_x Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADC_JOFR1 Reset value Reserved 0 0 0 JOFFSET1[11:0] 0 0 0 0 0 0 0 0 0 ADC_JOFR2 Reset value Reserved 0 0 0 JOFFSET2[11:0] 0 0 0 0 0 0 0 0 0 ADC_JOFR3 Reset value Reserved 0 0 0 JOFFSET3[11:0] 0 0 0 0 0 0 0 0 0 ADC_JOFR4 Reset value Reserved 0 0 0 JOFFSET4[11:0] 0 0 0 0 0 0 0 0 0 ADC_HTR Reset value Reserved 1 1 1 1 HT[11:0] 1 1 1 1 1 1 1 1 ADC_LTR Reset value Reserved 0 0 0 0 LT[11:0] 0 0 0 0 0 0 0 0 ADC_SQR1 Reset value Reserved 0 L[3:0] 0 0 0 0 0 0 0 Regular channel sequence SQx_x bits 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADC_SQR2 Regular channel sequence SQx_x bits Reserved Reserved Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADC_SQR3 Regular channel sequence SQx_x bits Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADC_JSQR Reset value Reserved JL[1:0] 0 0 0 0 0 0 Injected channel sequence JSQx_x bits 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADC_JDR1 Reset value Reserved 0 0 0 0 0 0 JDATA[15:0] 0 0 0 0 0 0 0 0 0 0 ADC_JDR2 Reset value Reserved 0 0 0 0 0 0 JDATA[15:0] 0 0 0 0 0 0 0 0 0 0 ADC_JDR3 Reset value Reserved 0 0 0 0 0 0 JDATA[15:0] 0 0 0 0 0 0 0 0 0 0 ADC_JDR4 Reset value Reserved 0 0 0 0 0 0 JDATA[15:0] 0 0 0 0 0 0 0 0 0 0 ADC_DR Reset value Reserved 0 0 0 0 0 Regular DATA[15:0] 0 0 0 0 0 0 0 0 0 0 0 CONT ADON
Analog-to-digital converter (ADC) <strong>RM0090</strong> Table 54. ADC register map and reset values (common ADC registers) Offset Register 31 0x00 0x04 0x08 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 OVR STRT JSTRT JEOC EOC AWD ADC_CSR Reset value Reserved 0 0 0 0 0 0 Reser ved 0 0 0 0 0 0 Reser ved 0 0 0 0 0 0 ADC3 ADC2 ADC1 ADC_CCR Reserved TSVREFE VBATE Reserved Refer to Table 2 on page 53 for the register boundary addresses. 305/1416 Doc ID 018909 Rev 3 ADCPRE[1:0] DMA[1:0] OVR STRT DDS Re se rv ed JSTRT JEOC EOC AWD OVR STRT DELAY [3:0] Reserved JSTRT JEOC EOC AWD MULTI [4:0] Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADC_CDR Regular DATA2[15:0] Regular DATA1[15:0] Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
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RM0090 Reference manual STM32F40x,
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Contents RM0090 3.5.3 Erase . . . .
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Contents RM0090 31.3.1 High-speed O
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Contents RM0090 33.2 Reference ARM
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List of tables RM0090 List of table
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List of tables RM0090 Table 98. Tra
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List of tables RM0090 Table 192. NO
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List of figures RM0090 Figure 49. A
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List of figures RM0090 Figure 151.
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Documentation conventions RM0090 1
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Memory and bus architecture RM0090
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Embedded Flash memory interface RM0
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CRC calculation unit RM0090 Bits 7:
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Power control (PWR) RM0090 Figure 7
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Power control (PWR) RM0090 When the
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Power control (PWR) RM0090 mode (se
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Power control (PWR) RM0090 A PVDO f
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Power control (PWR) RM0090 5.3.3 Sl
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Power control (PWR) RM0090 If an ac
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Power control (PWR) RM0090 I/O stat
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Power control (PWR) RM0090 Safe RTC
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Power control (PWR) RM0090 Bit 4 PV
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Power control (PWR) RM0090 5.4.3 PW
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DMA controller (DMA) RM0090 9 DMA c
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DMA controller (DMA) RM0090 9.3 DMA
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DMA controller (DMA) RM0090 Figure
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DMA controller (DMA) RM0090 Table 3
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DMA controller (DMA) RM0090 In dire
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DMA controller (DMA) RM0090 Figure
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DMA controller (DMA) RM0090 memory
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DMA controller (DMA) RM0090 9.3.11
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DMA controller (DMA) RM0090 9.4 DMA
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DMA controller (DMA) RM0090 9.5.5 D
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DMA controller (DMA) RM0090 15 14 1
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Interrupts and events RM0090 Table
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Interrupts and events RM0090 Table
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Independent watchdog (IWDG) RM0090
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Window watchdog (WWDG) RM0090 19 Wi
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Window watchdog (WWDG) RM0090 case,
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Window watchdog (WWDG) RM0090 19.6.
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Hash processor (HASH) RM0090 Proced
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Hash processor (HASH) RM0090 Bit 12
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Debug support (DBG) RM0090 33 Debug
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Debug support (DBG) RM0090 Note: No
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Debug support (DBG) RM0090 31 30 29
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Device electronic signature RM0090
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A ADC_CCR . . . . . . . . . . . . .
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DMA_SxM1AR . . . . . . . . . . . .
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HASH_SR . . . . . . . . . . . . . .
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RNG_DR . . . . . . . . . . . . . .
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Revision history RM0090 Revision hi
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Revision history RM0090 Table 238.
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RM0090: Reference manual - STMicroelectronics

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