RM0090: Reference manual - STMicroelectronics

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<strong>RM0090</strong> Memory and bus architecture 2.1.5 S5: DMA peripheral bus This bus connects the DMA peripheral master bus interface to the BusMatrix. This bus is used by the DMA to access AHB peripherals or to perform memory-to-memory transfers. The targets of this bus are the AHB and APB peripherals plus data memories: internal SRAM and external memories through the FSMC. 2.1.6 S6: Ethernet DMA bus This bus connects the Ethernet DMA master interface to the BusMatrix. This bus is used by the Ethernet DMA to load/store data to a memory. The targets of this bus are data memories: internal SRAMs (112, 64, and 16 Kbytes) and external memories through the FSMC. 2.1.7 S7: USB OTG HS DMA bus This bus connects the USB OTG HS DMA master interface to the BusMatrix. This bus is used by the USB OTG DMA to load/store data to a memory. The targets of this bus are data memories: internal SRAMs (112, 64, and 16 Kbytes) and external memories through the FSMC. 2.1.8 BusMatrix The BusMatrix manages the access arbitration between masters. The arbitration uses a round-robin algorithm. 2.1.9 AHB/APB bridges (APB) The two AHB/APB bridges, APB1 and APB2, provide full synchronous connections between the AHB and the two APB buses, allowing flexible selection of the peripheral frequency. Refer to the device datasheets for more details on APB1 and APB2 maximum frequencies, and to Table 2 on page 53 for the address mapping of AHB and APB peripherals. After each device reset, all peripheral clocks are disabled (except for the SRAM and Flash memory interface). Before using a peripheral you have to enable its clock in the RCC_AHBxENR or RCC_APBxENR register. Note: When a 16- or an 8-bit access is performed on an APB register, the access is transformed into a 32-bit access: the bridge duplicates the 16- or 8-bit data to feed the 32-bit vector. 2.2 Memory organization Program memory, data memory, registers and I/O ports are organized within the same linear 4 Gbyte address space. The bytes are coded in memory in little endian format. The lowest numbered byte in a word is considered the word’s least significant byte and the highest numbered byte, the word’s most significant. For the detailed mapping of peripheral registers, please refer to the related chapters. The addressable memory space is divided into 8 main blocks, each of 512 MB. Doc ID 018909 Rev 3 52/1416
Memory and bus architecture <strong>RM0090</strong> All the memory areas that are not allocated to on-chip memories and peripherals are considered “Reserved”). Refer to the memory map figure in the product datasheet. 2.3 Memory map See the datasheet corresponding to your device for a comprehensive diagram of the memory map. Table 2 gives the boundary addresses of the peripherals available in all STM32F4xx devices. Table 2. STM32F4xx register boundary addresses Boundary address Peripheral Bus Register map 0xA000 0000 - 0xA000 0FFF FSMC control register AHB3 Section 32.6.9: FSMC register map on page 1365 0x5006 0800 - 0X5006 0BFF RNG 0x5006 0000 - 0X5006 03FF CRYP AHB2 Section 20.6.13: CRYP register map on page 586 0x5005 0000 - 0X5005 03FF DCMI Section 13.8.12: DCMI register map on page 347 53/1416 Doc ID 018909 Rev 3 Section 21.4.4: RNG register map on page 593 0x5006 0400 - 0X5006 07FF HASH Section 22.4.9: HASH register map on page 617 0x5000 0000 - 0X5003 FFFF USB OTG FS 0x4004 0000 - 0x4007 FFFF USB OTG HS 0x4002 9000 - 0x4002 93FF 0x4002 8C00 - 0x4002 8FFF 0x4002 8800 - 0x4002 8BFF 0x4002 8400 - 0x4002 87FF 0x4002 8000 - 0x4002 83FF ETHERNET MAC 0x4002 6400 - 0x4002 67FF DMA2 0x4002 6000 - 0x4002 63FF DMA1 0x4002 4000 - 0x4002 4FFF BKPSRAM 0x4002 3C00 - 0x4002 3FFF Flash interface register Section 30.16.6: OTG_FS register map on page 1102 Section 31.12.6: OTG_HS register map on page 1244 Section 29.8.5: Ethernet register maps on page 1013 Section 9.5.11: DMA register map on page 243 Section 3.8: Flash interface registers 0x4002 3800 - 0x4002 3BFF RCC Section 6.3.32: RCC register map on page 181 0x4002 3000 - 0x4002 33FF CRC AHB1 Section 4.4.4: CRC register map on page 89 0x4002 2000 - 0x4002 23FF GPIOI 0x4002 1C00 - 0x4002 1FFF GPIOH 0x4002 1800 - 0x4002 1BFF GPIOG 0x4002 1400 - 0x4002 17FF GPIOF 0x4002 1000 - 0x4002 13FF GPIOE Section 7.4.11: GPIO register map on page 203 0X4002 0C00 - 0x4002 0FFF GPIOD 0x4002 0800 - 0x4002 0BFF GPIOC 0x4002 0400 - 0x4002 07FF GPIOB 0x4002 0000 - 0x4002 03FF GPIOA
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Debug support (DBG) RM0090 33 Debug
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Debug support (DBG) RM0090 Bit 20:1
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Device electronic signature RM0090
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A ADC_CCR . . . . . . . . . . . . .
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DMA_SxM1AR . . . . . . . . . . . .
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HASH_SR . . . . . . . . . . . . . .
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RNG_DR . . . . . . . . . . . . . .
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Revision history RM0090 Revision hi
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Revision history RM0090 Table 238.
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RM0090: Reference manual - STMicroelectronics

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