RM0090: Reference manual - STMicroelectronics

Flexible static memory controller (FSMC) RM0090
Figure 420. Synchronous multiplexed read mode - NOR, PSRAM (CRAM)
HCLK
CLK
A[25:16]
NEx
NOE
NWE
NADV
High
NWAIT
(WAITCFG = 1)
A/D[15:0]
1 clock
cycle
addr[25:16]
Memory transaction = burst of 4 half words
Addr[15:0] data data
1 clock
cycle
(DATALAT + 2) inserted wait state
CLK cycles
Data strobes
1. Byte lane outputs BL are not shown; for NOR access, they are held high, and, for PSRAM (CRAM) access, they are held
low.
Table 209. FSMC_BCRx bit fields
Bit No. Bit name Value to set
31-20 0x0000
19 CBURSTRW No effect on synchronous read
18-15 0x0
1341/1416 Doc ID 018909 Rev 3
data data
Data strobes
14 EXTMOD 0x0
13 WAITEN
When high, the first data after latency period is taken as always
valid, regardless of the wait from memory value
12 WREN no effect on synchronous read
11 WAITCFG to be set according to memory
10 WRAPMOD no effect
9 WAITPOL to be set according to memory
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