09.12.2012 Views

RM0090: Reference manual - STMicroelectronics

RM0090: Reference manual - STMicroelectronics

RM0090: Reference manual - STMicroelectronics

SHOW MORE
SHOW LESS

You also want an ePaper? Increase the reach of your titles

YUMPU automatically turns print PDFs into web optimized ePapers that Google loves.

<strong>RM0090</strong> USB on-the-go full-speed (OTG_FS)<br />

Bit 17 NAKSTS: NAK status<br />

Indicates the following:<br />

0: The core is transmitting non-NAK handshakes based on the FIFO status<br />

1: The core is transmitting NAK handshakes on this endpoint.<br />

When this bit is set, either by the application or core, the core stops transmitting data, even<br />

if there are data available in the TxFIFO. Irrespective of this bit’s setting, the core always<br />

responds to SETUP data packets with an ACK handshake.<br />

Bit 16 Reserved, must be kept at reset value.<br />

Bit 15 USBAEP: USB active endpoint<br />

This bit is always set to 1, indicating that control endpoint 0 is always active in all<br />

configurations and interfaces.<br />

Bits 14:2 Reserved, must be kept at reset value.<br />

Bits 1:0 MPSIZ: Maximum packet size<br />

The application must program this field with the maximum packet size for the current logical<br />

endpoint.<br />

00: 64 bytes<br />

01: 32 bytes<br />

10: 16 bytes<br />

11: 8 bytes<br />

OTG device endpoint-x control register (OTG_FS_DIEPCTLx) (x = 1..3, where<br />

x = Endpoint_number)<br />

Address offset: 0x900 + (Endpoint_number × 0x20)<br />

Reset value: 0x0000 0000<br />

The application uses this register to control the behavior of each logical endpoint other than<br />

endpoint 0.<br />

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0<br />

EPENA<br />

EPDIS<br />

SODDFRM<br />

SD0PID/SEVNFRM<br />

SNAK<br />

CNAK<br />

TXFNUM<br />

Stall<br />

rs rs w w w w rw rw rw rw rw/<br />

rs<br />

Reserved<br />

EPTYP<br />

NAKSTS<br />

EONUM/DPID<br />

USBAEP<br />

Reserved<br />

MPSIZ<br />

rw rw r r rw rw rw rw rw rw rw rw rw rw rw rw<br />

Bit 31 EPENA: Endpoint enable<br />

The application sets this bit to start transmitting data on an endpoint.<br />

The core clears this bit before setting any of the following interrupts on this endpoint:<br />

– SETUP phase done<br />

– Endpoint disabled<br />

– Transfer completed<br />

Doc ID 018909 Rev 3 1088/1416

Hooray! Your file is uploaded and ready to be published.

Saved successfully!

Ooh no, something went wrong!