RM0090: Reference manual - STMicroelectronics

RM0090 General-purpose timers (TIM9 to TIM14)
Figure 167. Counter timing diagram with prescaler division change from 1 to 2
Figure 168. Counter timing diagram with prescaler division change from 1 to 4
16.4.2 Counter modes
Upcounting mode
CK_PSC
CEN
Timer clock = CK_CNT
Counter register
Update event (UEV)
F7
F8 F9 FA FB FC
Prescaler control register 0 1
Write a new value in TIMx_PSC
Prescaler buffer 0 1
Prescaler counter 0 0 1 0 1 0 1 0 1
CK_PSC
CEN
Timer clock = CK_CNT
Counter register
Update event (UEV)
F7
In upcounting mode, the counter counts from 0 to the auto-reload value (content of the
TIMx_ARR register), then restarts from 0 and generates a counter overflow event.
Setting the UG bit in the TIMx_EGR register (by software or by using the slave mode
controller on TIM9 and TIM12) also generates an update event.
The UEV event can be disabled by software by setting the UDIS bit in the TIMx_CR1
register. This is to avoid updating the shadow registers while writing new values in the
preload registers. Then no update event occurs until the UDIS bit has been written to 0.
However, the counter restarts from 0, as well as the counter of the prescaler (but the
prescale rate does not change). In addition, if the URS bit (update request selection) in
TIMx_CR1 register is set, setting the UG bit generates an update event UEV but without
00
01 02 03
F8 F9 FA FB FC 00
01
Prescaler control register 0 3
Write a new value in TIMx_PSC
Prescaler buffer 0 3
Prescaler counter 0 0 1 2 3 0 1 2 3
Doc ID 018909 Rev 3 482/1416