RM0090: Reference manual - STMicroelectronics

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<strong>RM0090</strong> Universal synchronous asynchronous receiver transmitter (USART) Table 110. Error calculation for programmed baud rates at f PCLK = 8 MHz or f PCLK = 16 MHz, oversampling by 16 (1) (continued) 9. 921.6 KBps NA NA NA 941.176 KBps 1.0625 2.12% 10. 1.792 MBps NA NA NA NA NA NA 11. 1.8432 MBps NA NA NA NA NA NA 12. 3.584 MBps NA NA NA NA NA NA 13. 3.6864 MBps NA NA NA NA NA NA 14. 7.168 MBps NA NA NA NA NA NA 15. 7.3728 MBps NA NA NA NA NA NA 1. The lower the CPU clock the lower the accuracy for a particular baud rate. The upper limit of the achievable baud rate can be fixed with these data. Table 111. Error calculation for programmed baud rates at f PCLK = 8 MHz or f PCLK = 16 MHz, oversampling by 8 (1) Oversampling by 8 (OVER8=1) Baud rate f PCLK = 8 MHz f PCLK = 16 MHz S.No Desired Actual Oversampling by 16 (OVER8=0) Baud rate f PCLK = 8 MHz f PCLK = 16 MHz S.No Desired Actual Value programmed in the baud rate register Value programmed in the baud rate register % Error = (Calculated - Desired)B.Rate /Desired B.Rate % Error = (Calculated - Desired)B.Rate /Desired B.Rate Actual Actual Value programmed in the baud rate register Value programmed in the baud rate register % Error 1. 2.4 KBps 2.400 KBps 416.625 0.01% 2.400 KBps 833.375 0.00% 2. 9.6 KBps 9.604 KBps 104.125 0.04% 9.598 KBps 208.375 0.02% 3. 19.2 KBps 19.185 KBps 52.125 0.08% 19.208 KBps 104.125 0.04% 4. 57.6 KBps 57.557 KBps 17.375 0.08% 57.554 KBps 34.750 0.08% 5. 115.2 KBps 115.942 KBps 8.625 0.64% 115.108 KBps 17.375 0.08% 6. 230.4 KBps 228.571 KBps 4.375 0.79% 231.884 KBps 8.625 0.64% 7. 460.8 KBps 470.588 KBps 2.125 2.12% 457.143 KBps 4.375 0.79% 8. 896 KBps 888.889 KBps 1.125 0.79% 888.889 KBps 2.250 0.79% 9. 921.6 KBps 888.889 KBps 1.125 3.55% 941.176 KBps 2.125 2.12% 10. 1.792 MBps NA NA NA 1.7777 MBps 1.125 0.79% 11. 1.8432 MBps NA NA NA 1.7777 MBps 1.125 3.55% 12. 3.584 MBps NA NA NA NA NA NA 13. 3.6864 MBps NA NA NA NA NA NA 14. 7.168 MBps NA NA NA NA NA NA 15. 7.3728 MBps NA NA NA NA NA NA % Error Doc ID 018909 Rev 3 756/1416
Universal synchronous asynchronous receiver transmitter (USART) <strong>RM0090</strong> 1. The lower the CPU clock the lower the accuracy for a particular baud rate. The upper limit of the achievable baud rate can be fixed with these data. Table 112. Error calculation for programmed baud rates at f PCLK = 30 MHz or f PCLK = 60 MHz, oversampling by 16 (1)(2) Oversampling by 16 (OVER8=0) Baud rate f PCLK = 30 MHz f PCLK = 60 MHz S.No Desired Actual Value programmed in the baud rate register % Error = (Calculated - Desired)B.Rate /Desired B.Rate 757/1416 Doc ID 018909 Rev 3 Actual Value programmed in the baud rate register % Error 1. 2.4 KBps 2.400 KBps 781.2500 0.00% 2.400 KBps 1562.5000 0.00% 2. 9.6 KBps 9.600 KBps 195.3125 0.00% 9.600 KBps 390.6250 0.00% 3. 19.2 KBps 19.194 KBps 97.6875 0.03% 19.200 KBps 195.3125 0.00% 4. 57.6 KBps 57.582KBps 32.5625 0.03% 57.582 KBps 65.1250 0.03% 5. 115.2 KBps 115.385 KBps 16.2500 0.16% 115.163 KBps 32.5625 0.03% 6. 230.4 KBps 230.769 KBps 8.1250 0.16% 230.769KBps 16.2500 0.16% 7. 460.8 KBps 461.538 KBps 4.0625 0.16% 461.538 KBps 8.1250 0.16% 8. 896 KBps 909.091 KBps 2.0625 1.46% 895.522 KBps 4.1875 0.05% 9. 921.6 KBps 909.091 KBps 2.0625 1.36% 923.077 KBps 4.0625 0.16% 10. 1.792 MBps 1.1764 MBps 1.0625 1.52% 1.8182 MBps 2.0625 1.36% 11. 1.8432 MBps 1.8750 MBps 1.0000 1.73% 1.8182 MBps 2.0625 1.52% 12. 3.584 MBps NA NA NA 3.2594 MBps 1.0625 1.52% 13. 3.6864 MBps NA NA NA 3.7500 MBps 1.0000 1.73% 14. 7.168 MBps NA NA NA NA NA NA 15. 7.3728 MBps NA NA NA NA NA NA 1. The lower the CPU clock the lower the accuracy for a particular baud rate. The upper limit of the achievable baud rate can be fixed with these data. 2. Only USART1 and USART6 are clocked with PCLK2. Other USARTs are clocked with PCLK1. Refer to the device datasheets for the maximum values for PCLK1 and PCLK2. Table 113. Error calculation for programmed baud rates at fPCLK = 30 MHz or fPCLK = 60 MHz, (1) (2) oversampling by 8 Oversampling by 8 (OVER8=1) Baud rate f PCLK = 30 MHz f PCLK =60 MHz S.No Desired Actual Value programmed in the baud rate register % Error = (Calculated - Desired)B.Rate /Desired B.Rate Actual Value programmed in the baud rate register % Error 1. 2.4 KBps 2.400 KBps 1562.5000 0.00% 2.400 KBps 3125.0000 0.00% 2. 9.6 KBps 9.600 KBps 390.6250 0.00% 9.600 KBps 781.2500 0.00%
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RM0090 Reference manual STM32F40x,
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Contents RM0090 3.5.3 Erase . . . .
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Contents RM0090 6.3.1 RCC clock con
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Contents RM0090 7.4.7 GPIO port bit
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Contents RM0090 10.3.4 Falling trig
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Contents RM0090 12.4.2 Independent
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Contents RM0090 14.3.3 Repetition c
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Contents RM0090 15.4.12 TIMx auto-r
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Contents RM0090 17.4.6 TIM6&TIM7 co
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Contents RM0090 22.1 HASH introduct
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Contents RM0090 24.3.3 Tx mailboxes
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Contents RM0090 26.3.14 Hardware fl
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Contents RM0090 28.4.13 SD I/O mode
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Contents RM0090 29.7 Ethernet inter
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Contents RM0090 31.3.1 High-speed O
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Contents RM0090 33.2 Reference ARM
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List of tables RM0090 List of table
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List of tables RM0090 Table 98. Tra
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List of tables RM0090 Table 192. NO
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List of figures RM0090 Figure 49. A
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List of figures RM0090 Figure 151.
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Documentation conventions RM0090 1
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Memory and bus architecture RM0090
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Embedded Flash memory interface RM0
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CRC calculation unit RM0090 Bits 7:
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Power control (PWR) RM0090 Figure 7
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Power control (PWR) RM0090 When the
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Power control (PWR) RM0090 mode (se
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Power control (PWR) RM0090 A PVDO f
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Power control (PWR) RM0090 5.3.3 Sl
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Power control (PWR) RM0090 If an ac
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Power control (PWR) RM0090 I/O stat
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Power control (PWR) RM0090 Safe RTC
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Power control (PWR) RM0090 Bit 4 PV
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Power control (PWR) RM0090 5.4.3 PW
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DMA controller (DMA) RM0090 9 DMA c
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DMA controller (DMA) RM0090 9.3 DMA
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DMA controller (DMA) RM0090 Figure
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DMA controller (DMA) RM0090 Table 3
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DMA controller (DMA) RM0090 In dire
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DMA controller (DMA) RM0090 Figure
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DMA controller (DMA) RM0090 memory
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DMA controller (DMA) RM0090 9.3.11
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DMA controller (DMA) RM0090 9.4 DMA
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DMA controller (DMA) RM0090 9.5.5 D
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Interrupts and events RM0090 Table
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Basic timers (TIM6&TIM7) RM0090 17
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Window watchdog (WWDG) RM0090 19.6
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Window watchdog (WWDG) RM0090 19.6.
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Debug support (DBG) RM0090 33 Debug
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Debug support (DBG) RM0090 Note: No
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Debug support (DBG) RM0090 33.9 AHB
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Debug support (DBG) RM0090 33.11 Ca
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Debug support (DBG) RM0090 For this
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Debug support (DBG) RM0090 33.15.3
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Debug support (DBG) RM0090 31 30 29
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Debug support (DBG) RM0090 Bit 20:1
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Device electronic signature RM0090
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A ADC_CCR . . . . . . . . . . . . .
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DMA_SxM1AR . . . . . . . . . . . .
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HASH_SR . . . . . . . . . . . . . .
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RNG_DR . . . . . . . . . . . . . .
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Revision history RM0090 Revision hi
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Revision history RM0090 Table 238.
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show all

RM0090: Reference manual - STMicroelectronics

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