RM0090: Reference manual - STMicroelectronics

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<strong>RM0090</strong> Flexible static memory controller (FSMC) The differences with mode1 are the toggling of NADV, NOE that goes on toggling after NADV changes and the independent read and write timings. Table 204. FSMC_BCRx bit fields Bit No. Bit name Value to set 31-16 0x0000 15 ASYNCWAIT Set to 1 if the memory supports this feature. Otherwise keep at 0. 14 EXTMOD 0x1 13-10 0x0 9 WAITPOL Meaningful only if bit 15 is 1 8 BURSTEN 0x0 7 - 6 FACCEN Set according to memory support 5-4 MWID As needed 3-2 MTYP As needed 1 MUXEN 0x0 0 MBKEN 0x1 Table 205. FSMC_BTRx bit fields Bit No. Bit name Value to set 31-30 0x0 29-28 ACCMOD 0x2 27-20 0x000 19-16 BUSTURN Time between NEx high to NEx low (BUSTURN HCLK) 15-8 DATAST Duration of the second access phase (DATAST HCLK cycles) in read. 7-4 ADDHLD 3-0 ADDSET Table 206. FSMC_BWTRx bit fields Duration of the middle phase of the read access (ADDHLD HCLK cycles) Duration of the first access phase (ADDSETHCLK cycles) in read. Minimum value for ADDSET is 1. Bit No. Bit name Value to set 31-30 0x0 29-28 ACCMOD 0x2 27-20 0x000 19-16 BUSTURN Time between NEx high to NEx low (BUSTURN HCLK) 15-8 DATAST Duration of the second access phase (DATAST+1 HCLK cycles) in write. Doc ID 018909 Rev 3 1334/1416
Flexible static memory controller (FSMC) <strong>RM0090</strong> Table 206. FSMC_BWTRx bit fields (continued) Bit No. Bit name Value to set 7-4 ADDHLD 3-0 ADDSET Muxed mode - multiplexed asynchronous access to NOR Flash memory Figure 415. Multiplexed read accesses A[25:16] NADV NEx NOE NWE AD[15:0] High 1335/1416 Doc ID 018909 Rev 3 Duration of the middle phase of the write access (ADDHLD HCLK cycles) Duration of the first access phase (ADDSET HCLK cycles) in write. Minimum value for ADDSET is 1. Lower address Memory transaction ADDSET DATAST HCLK cycles ADDHLD HCLK cycles HCLK cycles data driven by memory ai15568
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RM0090 Reference manual STM32F40x,
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Contents RM0090 3.5.3 Erase . . . .
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Contents RM0090 6.3.1 RCC clock con
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Contents RM0090 7.4.7 GPIO port bit
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Contents RM0090 10.3.4 Falling trig
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Contents RM0090 12.4.2 Independent
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Contents RM0090 14.3.3 Repetition c
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Contents RM0090 15.4.12 TIMx auto-r
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Contents RM0090 17.4.6 TIM6&TIM7 co
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Contents RM0090 22.1 HASH introduct
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Contents RM0090 24.3.3 Tx mailboxes
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Contents RM0090 26.3.14 Hardware fl
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Contents RM0090 28.4.13 SD I/O mode
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Contents RM0090 29.7 Ethernet inter
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Contents RM0090 31.3.1 High-speed O
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Contents RM0090 33.2 Reference ARM
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List of tables RM0090 List of table
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List of tables RM0090 Table 98. Tra
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List of tables RM0090 Table 192. NO
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List of figures RM0090 Figure 49. A
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List of figures RM0090 Figure 151.
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Documentation conventions RM0090 1
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Memory and bus architecture RM0090
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Embedded Flash memory interface RM0
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CRC calculation unit RM0090 4 CRC c
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CRC calculation unit RM0090 Bits 7:
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Power control (PWR) RM0090 Figure 7
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Power control (PWR) RM0090 When the
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Power control (PWR) RM0090 mode (se
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Power control (PWR) RM0090 A PVDO f
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Power control (PWR) RM0090 5.3.3 Sl
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Power control (PWR) RM0090 If an ac
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Power control (PWR) RM0090 I/O stat
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Power control (PWR) RM0090 Safe RTC
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Power control (PWR) RM0090 Bit 4 PV
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Power control (PWR) RM0090 5.4.3 PW
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Reset and clock control for (RCC) R
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DMA controller (DMA) RM0090 9 DMA c
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DMA controller (DMA) RM0090 9.3 DMA
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DMA controller (DMA) RM0090 Figure
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DMA controller (DMA) RM0090 Table 3
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DMA controller (DMA) RM0090 In dire
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DMA controller (DMA) RM0090 Figure
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DMA controller (DMA) RM0090 memory
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DMA controller (DMA) RM0090 9.3.11
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DMA controller (DMA) RM0090 9.4 DMA
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DMA controller (DMA) RM0090 Bits 25
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DMA controller (DMA) RM0090 9.5.5 D
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DMA controller (DMA) RM0090 Bits 8
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DMA controller (DMA) RM0090 15 14 1
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Interrupts and events RM0090 10 Int
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Interrupts and events RM0090 Table
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Interrupts and events RM0090 genera
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Interrupts and events RM0090 10.3 E
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Interrupts and events RM0090 15 14
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Basic timers (TIM6&TIM7) RM0090 17
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Basic timers (TIM6&TIM7) RM0090 Fig
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Basic timers (TIM6&TIM7) RM0090 17.
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Independent watchdog (IWDG) RM0090
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Independent watchdog (IWDG) RM0090
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Window watchdog (WWDG) RM0090 19 Wi
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Window watchdog (WWDG) RM0090 case,
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Window watchdog (WWDG) RM0090 19.6
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Window watchdog (WWDG) RM0090 19.6.
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Hash processor (HASH) RM0090 22.3 H
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Hash processor (HASH) RM0090 has le
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Hash processor (HASH) RM0090 The le
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Hash processor (HASH) RM0090 with v
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Hash processor (HASH) RM0090 Proced
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Hash processor (HASH) RM0090 Bit 12
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Hash processor (HASH) RM0090 22.4.2
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Hash processor (HASH) RM0090 Bit 3
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Hash processor (HASH) RM0090 HASH_H
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Hash processor (HASH) RM0090 Table
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Real-time clock (RTC) RM0090 RTC_TR
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Real-time clock (RTC) RM0090 Bit 3
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Page 1333: Flexible static memory controller (
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Debug support (DBG) RM0090 31 30 29
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Debug support (DBG) RM0090 Bit 20:1
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Device electronic signature RM0090
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A ADC_CCR . . . . . . . . . . . . .
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DMA_SxM1AR . . . . . . . . . . . .
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HASH_SR . . . . . . . . . . . . . .
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RNG_DR . . . . . . . . . . . . . .
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Revision history RM0090 Revision hi
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Revision history RM0090 Table 238.
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