RM0090: Reference manual - STMicroelectronics

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RM0090 Debug support (DBG) The ARM Cortex-M4F core provides integrated on-chip debug support. It is comprised of: ● SWJ-DP: Serial wire / JTAG debug port ● AHP-AP: AHB access port ● ITM: Instrumentation trace macrocell ● FPB: Flash patch breakpoint ● DWT: Data watchpoint trigger ● TPUI: Trace port unit interface (available on larger packages, where the corresponding pins are mapped) ● ETM: Embedded Trace Macrocell (available on larger packages, where the corresponding pins are mapped) It also includes debug features dedicated to the STM32F4xx: ● Flexible debug pinout assignment ● MCU debug box (support for low-power modes, control over peripheral clocks, etc.) Note: For further information on debug functionality supported by the ARM Cortex-M4F core, refer to the Cortex-M4F-r0p1 Technical Reference Manual and to the CoreSight Design Kit-r0p1 TRM (see Section 33.2: Reference ARM documentation). 33.2 Reference ARM documentation ● Cortex-M4F r0p1 Technical Reference Manual (TRM) (see Related documents on page 1) ● ARM Debug Interface V5 ● ARM CoreSight Design Kit revision r0p1 Technical Reference Manual 33.3 SWJ debug port (serial wire and JTAG) The STM32F4xx core integrates the Serial Wire / JTAG Debug Port (SWJ-DP). It is an ARM standard CoreSight debug port that combines a JTAG-DP (5-pin) interface and a SW-DP (2pin) interface. ● The JTAG Debug Port (JTAG-DP) provides a 5-pin standard JTAG interface to the AHP- AP port. ● The Serial Wire Debug Port (SW-DP) provides a 2-pin (clock + data) interface to the AHP-AP port. In the SWJ-DP, the two JTAG pins of the SW-DP are multiplexed with some of the five JTAG pins of the JTAG-DP. Doc ID 018909 Rev 3 1368/1416
Debug support (DBG) RM0090 Figure 425. SWJ debug port JTDO JTDI NJTRST JTMS/SWDIO JTCK/SWCLK TRACESWO (asynchronous trace) SWJ-DP TDO TDI nTRST SWD/JTAG select SWDITMS SWDO SWDOEN SWCLKTCK Figure 425 shows that the asynchronous TRACE output (TRACESWO) is multiplexed with TDO. This means that the asynchronous trace can only be used with SW-DP, not JTAG-DP. 33.3.1 Mechanism to select the JTAG-DP or the SW-DP By default, the JTAG-Debug Port is active. If the debugger host wants to switch to the SW-DP, it must provide a dedicated JTAG sequence on TMS/TCK (respectively mapped to SWDIO and SWCLK) which disables the JTAG-DP and enables the SW-DP. This way it is possible to activate the SWDP using only the SWCLK and SWDIO pins. This sequence is: 1. Send more than 50 TCK cycles with TMS (SWDIO) =1 2. Send the 16-bit sequence on TMS (SWDIO) = 0111100111100111 (MSB transmitted first) 3. Send more than 50 TCK cycles with TMS (SWDIO) =1 33.4 Pinout and debug port pins The STM32F4xx MCUs are available in various packages with different numbers of available pins. As a result, some functionality (ETM) related to pin availability may differ between packages. 1369/1416 Doc ID 018909 Rev 3 TDO TDI nTRST TCK TMS DBGDI DBGDO DBGDOEN DBGCLK JTAG-DP nPOTRST nPOTRST DBGRESETn SW-DP From power-on reset ai17139
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RM0090 Reference manual STM32F40x,
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Contents RM0090 3.5.3 Erase . . . .
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Contents RM0090 6.3.1 RCC clock con
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Contents RM0090 7.4.7 GPIO port bit
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Contents RM0090 10.3.4 Falling trig
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Contents RM0090 12.4.2 Independent
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Contents RM0090 14.3.3 Repetition c
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Contents RM0090 15.4.12 TIMx auto-r
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Contents RM0090 17.4.6 TIM6&TIM7 co
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Contents RM0090 22.1 HASH introduct
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Contents RM0090 24.3.3 Tx mailboxes
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Contents RM0090 28.4.13 SD I/O mode
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Contents RM0090 29.7 Ethernet inter
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Contents RM0090 31.3.1 High-speed O
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Contents RM0090 33.2 Reference ARM
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List of tables RM0090 List of table
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List of tables RM0090 Table 98. Tra
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List of tables RM0090 Table 192. NO
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List of figures RM0090 Figure 49. A
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List of figures RM0090 Figure 151.
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Documentation conventions RM0090 1
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Memory and bus architecture RM0090
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Embedded Flash memory interface RM0
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CRC calculation unit RM0090 4 CRC c
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CRC calculation unit RM0090 Bits 7:
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Power control (PWR) RM0090 Figure 7
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Power control (PWR) RM0090 When the
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Power control (PWR) RM0090 mode (se
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Power control (PWR) RM0090 A PVDO f
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Power control (PWR) RM0090 5.3.3 Sl
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Power control (PWR) RM0090 If an ac
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Power control (PWR) RM0090 I/O stat
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Power control (PWR) RM0090 Safe RTC
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Power control (PWR) RM0090 Bit 4 PV
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Power control (PWR) RM0090 5.4.3 PW
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Reset and clock control for (RCC) R
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DMA controller (DMA) RM0090 9 DMA c
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DMA controller (DMA) RM0090 9.3 DMA
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DMA controller (DMA) RM0090 Figure
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DMA controller (DMA) RM0090 Table 3
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DMA controller (DMA) RM0090 In dire
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DMA controller (DMA) RM0090 Figure
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DMA controller (DMA) RM0090 memory
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DMA controller (DMA) RM0090 9.3.11
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DMA controller (DMA) RM0090 9.4 DMA
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DMA controller (DMA) RM0090 Bits 25
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DMA controller (DMA) RM0090 9.5.5 D
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DMA controller (DMA) RM0090 Bits 8
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DMA controller (DMA) RM0090 15 14 1
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Interrupts and events RM0090 Table
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Interrupts and events RM0090 genera
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Interrupts and events RM0090 10.3 E
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Interrupts and events RM0090 15 14
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Basic timers (TIM6&TIM7) RM0090 17
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Basic timers (TIM6&TIM7) RM0090 Fig
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Basic timers (TIM6&TIM7) RM0090 17.
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Independent watchdog (IWDG) RM0090
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Independent watchdog (IWDG) RM0090
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Window watchdog (WWDG) RM0090 19 Wi
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Window watchdog (WWDG) RM0090 case,
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Window watchdog (WWDG) RM0090 19.6
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Window watchdog (WWDG) RM0090 19.6.
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Hash processor (HASH) RM0090 22.3 H
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Hash processor (HASH) RM0090 has le
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Hash processor (HASH) RM0090 The le
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Hash processor (HASH) RM0090 with v
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Hash processor (HASH) RM0090 Proced
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Hash processor (HASH) RM0090 Bit 12
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Hash processor (HASH) RM0090 22.4.2
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Hash processor (HASH) RM0090 Bit 3
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Hash processor (HASH) RM0090 HASH_H
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Hash processor (HASH) RM0090 Table
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Real-time clock (RTC) RM0090 23.2 R
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Real-time clock (RTC) RM0090 23.3.5
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Real-time clock (RTC) RM0090 RTC_TR
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Real-time clock (RTC) RM0090 window
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Page 1399 and 1400: Device electronic signature RM0090
Page 1401 and 1402: A ADC_CCR . . . . . . . . . . . . .
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Page 1411 and 1412: Revision history RM0090 Table 238.
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