RM0090: Reference manual - STMicroelectronics

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<strong>RM0090</strong> Secure digital input/output interface (SDIO) 28.9.13 SDIO mask register (SDIO_MASK) Address offset: 0x3C Reset value: 0x0000 0000 The interrupt mask register determines which status flags generate an interrupt request by setting the corresponding bit to 1b. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved CEATAENDIE SDIOITIE RXDAVLIE TXDAVLIE RXFIFOEIE TXFIFOEIE RXFIFOFIE TXFIFOFIE RXFIFOHFIE TXFIFOHEIE RXACTIE TXACTIE rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw Bits 31:24 Reserved, must be kept at reset value Bit 23 CEATAENDIE: CE-ATA command completion signal received interrupt enable Set and cleared by software to enable/disable the interrupt generated when receiving the CE-ATA command completion signal. 0: CE-ATA command completion signal received interrupt disabled 1: CE-ATA command completion signal received interrupt enabled Bit 22 SDIOITIE: SDIO mode interrupt received interrupt enable Set and cleared by software to enable/disable the interrupt generated when receiving the SDIO mode interrupt. 0: SDIO Mode Interrupt Received interrupt disabled 1: SDIO Mode Interrupt Received interrupt enabled Bit 21 RXDAVLIE: Data available in Rx FIFO interrupt enable Set and cleared by software to enable/disable the interrupt generated by the presence of data available in Rx FIFO. 0: Data available in Rx FIFO interrupt disabled 1: Data available in Rx FIFO interrupt enabled Bit 20 TXDAVLIE: Data available in Tx FIFO interrupt enable Set and cleared by software to enable/disable the interrupt generated by the presence of data available in Tx FIFO. 0: Data available in Tx FIFO interrupt disabled 1: Data available in Tx FIFO interrupt enabled Bit 19 RXFIFOEIE: Rx FIFO empty interrupt enable Set and cleared by software to enable/disable interrupt caused by Rx FIFO empty. 0: Rx FIFO empty interrupt disabled 1: Rx FIFO empty interrupt enabled Bit 18 TXFIFOEIE: Tx FIFO empty interrupt enable Set and cleared by software to enable/disable interrupt caused by Tx FIFO empty. 0: Tx FIFO empty interrupt disabled 1: Tx FIFO empty interrupt enabled Bit 17 RXFIFOFIE: Rx FIFO full interrupt enable Set and cleared by software to enable/disable interrupt caused by Rx FIFO full. 0: Rx FIFO full interrupt disabled 1: Rx FIFO full interrupt enabled CMDACTIE DBCKENDIE STBITERRIE Doc ID 018909 Rev 3 894/1416 DATAENDIE CMDSENTIE CMDRENDIE RXOVERRIE TXUNDERRIE DTIMEOUTIE CTIMEOUTIE DCRCFAILIE CCRCFAILIE
Secure digital input/output interface (SDIO) <strong>RM0090</strong> Bit 16 TXFIFOFIE: Tx FIFO full interrupt enable Set and cleared by software to enable/disable interrupt caused by Tx FIFO full. 0: Tx FIFO full interrupt disabled 1: Tx FIFO full interrupt enabled Bit 15 RXFIFOHFIE: Rx FIFO half full interrupt enable Set and cleared by software to enable/disable interrupt caused by Rx FIFO half full. 0: Rx FIFO half full interrupt disabled 1: Rx FIFO half full interrupt enabled Bit 14 TXFIFOHEIE: Tx FIFO half empty interrupt enable Set and cleared by software to enable/disable interrupt caused by Tx FIFO half empty. 0: Tx FIFO half empty interrupt disabled 1: Tx FIFO half empty interrupt enabled Bit 13 RXACTIE: Data receive acting interrupt enable Set and cleared by software to enable/disable interrupt caused by data being received (data receive acting). 0: Data receive acting interrupt disabled 1: Data receive acting interrupt enabled Bit 12 TXACTIE: Data transmit acting interrupt enable Set and cleared by software to enable/disable interrupt caused by data being transferred (data transmit acting). 0: Data transmit acting interrupt disabled 1: Data transmit acting interrupt enabled Bit 11 CMDACTIE: Command acting interrupt enable Set and cleared by software to enable/disable interrupt caused by a command being transferred (command acting). 0: Command acting interrupt disabled 1: Command acting interrupt enabled Bit 10 DBCKENDIE: Data block end interrupt enable Set and cleared by software to enable/disable interrupt caused by data block end. 0: Data block end interrupt disabled 1: Data block end interrupt enabled Bit 9 STBITERRIE: Start bit error interrupt enable Set and cleared by software to enable/disable interrupt caused by start bit error. 0: Start bit error interrupt disabled 1: Start bit error interrupt enabled Bit 8 DATAENDIE: Data end interrupt enable Set and cleared by software to enable/disable interrupt caused by data end. 0: Data end interrupt disabled 1: Data end interrupt enabled Bit 7 CMDSENTIE: Command sent interrupt enable Set and cleared by software to enable/disable interrupt caused by sending command. 0: Command sent interrupt disabled 1: Command sent interrupt enabled 895/1416 Doc ID 018909 Rev 3
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RM0090 Reference manual STM32F40x,
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Contents RM0090 3.5.3 Erase . . . .
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Contents RM0090 6.3.1 RCC clock con
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Contents RM0090 7.4.7 GPIO port bit
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Contents RM0090 10.3.4 Falling trig
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Contents RM0090 12.4.2 Independent
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Contents RM0090 14.3.3 Repetition c
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Contents RM0090 15.4.12 TIMx auto-r
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Contents RM0090 17.4.6 TIM6&TIM7 co
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Contents RM0090 22.1 HASH introduct
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Contents RM0090 24.3.3 Tx mailboxes
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Contents RM0090 26.3.14 Hardware fl
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Contents RM0090 28.4.13 SD I/O mode
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Contents RM0090 29.7 Ethernet inter
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Contents RM0090 31.3.1 High-speed O
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Contents RM0090 33.2 Reference ARM
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List of tables RM0090 List of table
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List of tables RM0090 Table 98. Tra
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List of tables RM0090 Table 192. NO
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List of figures RM0090 Figure 49. A
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List of figures RM0090 Figure 151.
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Documentation conventions RM0090 1
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Memory and bus architecture RM0090
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Embedded Flash memory interface RM0
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CRC calculation unit RM0090 4 CRC c
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CRC calculation unit RM0090 Bits 7:
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Power control (PWR) RM0090 Figure 7
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Power control (PWR) RM0090 When the
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Power control (PWR) RM0090 mode (se
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Power control (PWR) RM0090 A PVDO f
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Power control (PWR) RM0090 5.3.3 Sl
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Power control (PWR) RM0090 If an ac
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Power control (PWR) RM0090 I/O stat
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Power control (PWR) RM0090 Safe RTC
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Power control (PWR) RM0090 Bit 4 PV
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Power control (PWR) RM0090 5.4.3 PW
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Reset and clock control for (RCC) R
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System configuration controller (SY
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DMA controller (DMA) RM0090 9 DMA c
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DMA controller (DMA) RM0090 9.3 DMA
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DMA controller (DMA) RM0090 Figure
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DMA controller (DMA) RM0090 Table 3
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DMA controller (DMA) RM0090 In dire
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DMA controller (DMA) RM0090 Figure
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DMA controller (DMA) RM0090 memory
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DMA controller (DMA) RM0090 9.3.11
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DMA controller (DMA) RM0090 9.4 DMA
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DMA controller (DMA) RM0090 Bits 25
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DMA controller (DMA) RM0090 9.5.5 D
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DMA controller (DMA) RM0090 Bits 8
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DMA controller (DMA) RM0090 15 14 1
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Interrupts and events RM0090 10 Int
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Interrupts and events RM0090 Table
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Interrupts and events RM0090 genera
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Interrupts and events RM0090 10.3 E
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Interrupts and events RM0090 15 14
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Basic timers (TIM6&TIM7) RM0090 17
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Basic timers (TIM6&TIM7) RM0090 Fig
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Basic timers (TIM6&TIM7) RM0090 17.
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Independent watchdog (IWDG) RM0090
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Independent watchdog (IWDG) RM0090
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Window watchdog (WWDG) RM0090 19 Wi
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Window watchdog (WWDG) RM0090 case,
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Window watchdog (WWDG) RM0090 19.6
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Window watchdog (WWDG) RM0090 19.6.
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Cryptographic processor (CRYP) RM00
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Random number generator (RNG) RM009
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Hash processor (HASH) RM0090 22.3 H
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Hash processor (HASH) RM0090 has le
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Hash processor (HASH) RM0090 The le
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Hash processor (HASH) RM0090 with v
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Hash processor (HASH) RM0090 Proced
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Hash processor (HASH) RM0090 Bit 12
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Hash processor (HASH) RM0090 22.4.2
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Hash processor (HASH) RM0090 Bit 3
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Hash processor (HASH) RM0090 HASH_H
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Hash processor (HASH) RM0090 Table
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Real-time clock (RTC) RM0090 23.2 R
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Real-time clock (RTC) RM0090 The as
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Real-time clock (RTC) RM0090 23.3.5
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Real-time clock (RTC) RM0090 RTC_TR
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Real-time clock (RTC) RM0090 window
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Real-time clock (RTC) RM0090 The fo
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Real-time clock (RTC) RM0090 Sectio
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Real-time clock (RTC) RM0090 Bit 3
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Controller area network (bxCAN) RM0
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Debug support (DBG) RM0090 33 Debug
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Debug support (DBG) RM0090 Figure 4
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Debug support (DBG) RM0090 33.4.3 I
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Debug support (DBG) RM0090 Only the
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Debug support (DBG) RM0090 Table 22
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Debug support (DBG) RM0090 Note: No
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Debug support (DBG) RM0090 33.9 AHB
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Debug support (DBG) RM0090 33.11 Ca
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Debug support (DBG) RM0090 31 30 29
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Debug support (DBG) RM0090 Bit 20:1
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Device electronic signature RM0090
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A ADC_CCR . . . . . . . . . . . . .
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DMA_SxM1AR . . . . . . . . . . . .
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HASH_SR . . . . . . . . . . . . . .
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RNG_DR . . . . . . . . . . . . . .
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Revision history RM0090 Revision hi
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Revision history RM0090 Table 238.
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