RM0090: Reference manual - STMicroelectronics

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<strong>RM0090</strong> Real-time clock (RTC) Table 97. RTC register map and reset values (continued) Offset Register 31 0x20 0x24 0x28 0x2C 0x30 0x38 0x3C 0x40 0x44 0x48 0x50 to 0x9C RTC_ALRMBR MSK4 WDSEL DT [1:0] DU[3:0] MSK3 PM HT [1:0] HU[3:0] Refer to Table 2 on page 53 for the register boundary addresses. MSK2 MNT[2:0] MNU[3:0] Doc ID 018909 Rev 3 658/1416 MSK2 ST[2:0] SU[3:0] Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RTC_WPR Reserved KEY[7:0] Reset value 0 0 0 0 0 0 0 0 RTC_SSR Reserved SS[15:0] Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RTC_SHIFTR ADD1S Reserved SUBFS[14:0] Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RTC_TSTR Reserved PM HT[1:0] HU[3:0] Reserved MNT[2:0] MNU[3:0] Reserved ST[2:0] SU[3:0] Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RTC_TSSSR Reserved SS[15:0] Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RTC_ CALR Reserved CALP CALW8 CALW16 Reserved CALM[8:0] Reset value 0 0 0 0 0 0 0 0 0 0 0 0 RTC_TAFCR 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved ALARMOUTTYPE TSINSEL Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RTC_ ALRMASSR Reserved MASKSS[3:0] Reserved TAMP1INSEL TAMPPUDIS TAMPPRCH[1:0] TAMPFLT[1:0] TAMPFREQ[2:0] TAMPTS SS[14:0] Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RTC_ ALRMBSSR Reserved MASKSS[3:0] Reserved SS[14:0] Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RTC_BKP0R BKP[31:0] Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 to RTC_BKP19R BKP[31:0] Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reserved TAMP2TRG TAMP2E TAMPIE TAMP1ETRG TAMP1E
Controller area network (bxCAN) <strong>RM0090</strong> 24 Controller area network (bxCAN) This section applies to the whole STM32F4xx family, unless otherwise specified. 24.1 bxCAN introduction The Basic Extended CAN peripheral, named bxCAN, interfaces the CAN network. It supports the CAN protocols version 2.0A and B. It has been designed to manage a high number of incoming messages efficiently with a minimum CPU load. It also meets the priority requirements for transmit messages. For safety-critical applications, the CAN controller provides all hardware functions for supporting the CAN Time Triggered Communication option. 24.2 bxCAN main features ● Supports CAN protocol version 2.0 A, B Active ● Bit rates up to 1 Mbit/s ● Supports the Time Triggered Communication option Transmission ● Three transmit mailboxes ● Configurable transmit priority ● Time Stamp on SOF transmission Reception ● Two receive FIFOs with three stages ● Scalable filter banks: – 28 filter banks shared between CAN1 and CAN2 ● Identifier list feature ● Configurable FIFO overrun ● Time Stamp on SOF reception Time-triggered communication option ● Disable automatic retransmission mode ● 16-bit free running timer ● Time Stamp sent in last two data bytes Management ● Maskable interrupts ● Software-efficient mailbox mapping at a unique address space 659/1416 Doc ID 018909 Rev 3
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RM0090 Reference manual STM32F40x,
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Contents RM0090 3.5.3 Erase . . . .
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Contents RM0090 6.3.1 RCC clock con
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Contents RM0090 22.1 HASH introduct
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Contents RM0090 24.3.3 Tx mailboxes
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Contents RM0090 29.7 Ethernet inter
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Contents RM0090 31.3.1 High-speed O
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Contents RM0090 33.2 Reference ARM
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List of tables RM0090 List of table
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List of tables RM0090 Table 98. Tra
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List of tables RM0090 Table 192. NO
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List of figures RM0090 Figure 49. A
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List of figures RM0090 Figure 151.
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Documentation conventions RM0090 1
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Memory and bus architecture RM0090
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Power control (PWR) RM0090 When the
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Power control (PWR) RM0090 mode (se
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Power control (PWR) RM0090 A PVDO f
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Power control (PWR) RM0090 5.3.3 Sl
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Power control (PWR) RM0090 If an ac
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Power control (PWR) RM0090 I/O stat
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Power control (PWR) RM0090 Safe RTC
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Power control (PWR) RM0090 Bit 4 PV
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DMA controller (DMA) RM0090 9 DMA c
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DMA controller (DMA) RM0090 9.3 DMA
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DMA controller (DMA) RM0090 Figure
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DMA controller (DMA) RM0090 In dire
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Hash processor (HASH) RM0090 Proced
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Hash processor (HASH) RM0090 Bit 12
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Debug support (DBG) RM0090 33 Debug
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Device electronic signature RM0090
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A ADC_CCR . . . . . . . . . . . . .
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DMA_SxM1AR . . . . . . . . . . . .
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HASH_SR . . . . . . . . . . . . . .
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Revision history RM0090 Revision hi
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Revision history RM0090 Table 238.
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