RM0090: Reference manual - STMicroelectronics

RM0090 Flexible static memory controller (FSMC)
Table 192. NOR Flash/PSRAM supported memories and transactions (continued)
Device Mode R/W
PSRAM
(multiplexed
I/Os and
nonmultiplexed
I/Os)
SRAM and
ROM
32.5.3 General timing rules
Signals synchronization
Asynchronous R 8 16 Y
Asynchronous W 8 16 Y Use of byte lanes NBL[1:0]
Asynchronous R 16 16 Y
Asynchronous W 16 16 Y
Asynchronous R 32 16 Y
Asynchronous W 32 16 Y
Asynchronous
page
AHB
data
size
Memory
data size
Allowed/
not
allowed
Split into 2 FSMC
accesses
Split into 2 FSMC
accesses
R - 16 N Mode is not supported
Synchronous R 8 16 N
Synchronous R 16 16 Y
Synchronous R 32 16 Y
Synchronous W 8 16 Y Use of byte lanes NBL[1:0]
Synchronous W 16/32 16 Y
Asynchronous R 8 / 16 16 Y
Asynchronous W 8 / 16 16 Y Use of byte lanes NBL[1:0]
Asynchronous R 32 16 Y
Split into 2 FSMC
accesses
Asynchronous W 32 16 Y
Comments
Split into 2 FSMC
accesses.
Use of byte lanes NBL[1:0]
● All controller output signals change on the rising edge of the internal clock (HCLK)
● In synchronous mode (read or write), all output signals change on the rising edge of
HCLK. Whatever the CLKDIV value, all outputs change as follows:
– NOEL/NWEL/ NEL/NADVL/ NADVH /NBLL/ Address valid outputs change on the
falling edge of FSMC_CLK clock.
– NOEH/ NWEH / NEH/ NOEH/NBLH/ Address invalid outputs change on the rising
edge of FSMC_CLK clock .
Doc ID 018909 Rev 3 1322/1416