RM0090: Reference manual - STMicroelectronics

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<strong>RM0090</strong> Flexible static memory controller (FSMC) ECC result registers 2/3 (FSMC_ECCR2/3) Address offset: 0xA000 0000 + 0x54 + 0x20 * (x – 1), x = 2 or 3 Reset value: 0x0000 0000 These registers contain the current error correction code value computed by the ECC computation modules of the FSMC controller (one module per NAND Flash memory bank). When the CPU reads the data from a NAND Flash memory page at the correct address (refer to Section 32.6.6: Error correction code computation ECC (NAND Flash)), the data read from or written to the NAND Flash are processed automatically by ECC computation module. At the end of X bytes read (according to the ECCPS field in the FSMC_PCRx registers), the CPU must read the computed ECC value from the FSMC_ECCx registers, and then verify whether these computed parity data are the same as the parity value recorded in the spare area, to determine whether a page is valid, and, to correct it if applicable. The FSMC_ECCRx registers should be cleared after being read by setting the ECCEN bit to zero. For computing a new data block, the ECCEN bit must be set to one. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ECCx r Bits 31:0 ECCx: ECC result This field provides the value computed by the ECC computation logic. Table 219 hereafter describes the contents of these bit fields. Table 219. ECC result relevant bits ECCPS[2:0] Page size in bytes ECC bits 000 256 ECC[21:0] 001 512 ECC[23:0] 010 1024 ECC[25:0] 011 2048 ECC[27:0] 100 4096 ECC[29:0] 101 8192 ECC[31:0] Doc ID 018909 Rev 3 1364/1416
Flexible static memory controller (FSMC) <strong>RM0090</strong> 32.6.9 FSMC register map The following table summarizes the FSMC registers. Table 220. FSMC register map Offset Register 31 0xA000 0000 0xA000 0008 0xA000 0010 0xA000 0018 0xA000 0004 0xA000 000C 0xA000 0014 0xA000 001C 0xA000 0104 0xA000 010C 0xA000 0114 0xA000 011C 0xA000 0060 0xA000 0080 0xA000 00A0 0xA000 0064 0xA000 0084 0xA000 00A4 0xA000 0068 0xA000 0088 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 FSMC_BCR1 Reserved FSMC_BCR2 Reserved FSMC_BCR3 Reserved FSMC_BCR4 Reserved FSMC_BTR1 Res. ACCM OD FSMC_BTR2 Res. ACCM OD FSMC_BTR3 Res. ACCM OD FSMC_BTR4 Res. ACCM OD FSMC_BWTR1 Res. ACCM OD FSMC_BWTR2 Res. ACCM OD FSMC_BWTR3 Res. ACCM OD FSMC_BWTR4 Res. ACCM OD 1365/1416 Doc ID 018909 Rev 3 CBURSTRW CBURSTRW CBURSTRW CBURSTRW Reserved Reserved Reserved Reserved ASYNCWAIT EXTMOD ASYNCWAIT EXTMOD ASYNCWAIT EXTMOD ASYNCWAIT EXTMOD WAITEN WREN WAITEN WREN WAITEN WREN WAITEN WREN WAITCFG WRAPMOD WAITCFG WRAPMOD WAITCFG WRAPMOD WAITCFG WRAPMOD WAITPOL BURSTEN Reserved FACCEN WAITPOL BURSTEN WAITPOL BURSTEN WAITPOL BURSTEN Reserved FACCEN Reserved FACCEN Reserved FACCEN DATLAT CLKDIV BUSTURN DATAST ADDHLD ADDSET DATLAT CLKDIV BUSTURN DATAST ADDHLD ADDSET DATLAT CLKDIV BUSTURN DATAST ADDHLD ADDSET DATLAT CLKDIV BUSTURN DATAST ADDHLD ADDSET DATLAT CLKDIV BUSTURN DATAST ADDHLD ADDSET DATLAT CLKDIV BUSTURN DATAST ADDHLD ADDSET DATLAT CLKDIV BUSTURN DATAST ADDHLD ADDSET DATLAT CLKDIV BUSTURN DATAST ADDHLD ADDSET FSMC_PCR2 Reserved ECCPS TAR TCLR Res. FSMC_PCR3 Reserved ECCPS TAR TCLR Res. FSMC_PCR4 Reserved ECCPS TAR TCLR Res. FSMC_SR2 Reserved FSMC_SR3 Reserved FSMC_SR4 Reserved FSMC_PMEM2 MEMHIZx MEMHOLDx MEMWAITx MEMSETx FSMC_PMEM3 MEMHIZx MEMHOLDx MEMWAITx MEMSETx ECCEN ECCEN ECCEN FEMPT IFEN FEMPT IFEN FEMPT IFEN MWID MWID MWID MWID PWID PWID PWID PTYP PTYP PTYP ILEN IREN ILEN IREN ILEN IREN MTYP MTYP MTYP MTYP PBKEN PBKEN PBKEN IFS ILS IFS ILS IFS ILS MUXEN MBKEN MUXEN MBKEN MUXEN MBKEN MUXEN MBKEN PWAITEN Reserved PWAITEN Reserved PWAITEN Reserved IRS IRS IRS
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RM0090 Reference manual STM32F40x,
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Contents RM0090 3.5.3 Erase . . . .
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Contents RM0090 6.3.1 RCC clock con
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Contents RM0090 29.7 Ethernet inter
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Contents RM0090 31.3.1 High-speed O
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Contents RM0090 33.2 Reference ARM
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List of tables RM0090 List of table
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List of tables RM0090 Table 98. Tra
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List of tables RM0090 Table 192. NO
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List of figures RM0090 Figure 49. A
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List of figures RM0090 Figure 151.
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Documentation conventions RM0090 1
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Memory and bus architecture RM0090
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CRC calculation unit RM0090 Bits 7:
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Power control (PWR) RM0090 Figure 7
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Power control (PWR) RM0090 When the
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Power control (PWR) RM0090 mode (se
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DMA controller (DMA) RM0090 9 DMA c
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DMA controller (DMA) RM0090 9.3 DMA
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DMA controller (DMA) RM0090 Table 3
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DMA controller (DMA) RM0090 In dire
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DMA controller (DMA) RM0090 memory
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Page 1401 and 1402: A ADC_CCR . . . . . . . . . . . . .
Page 1403 and 1404: DMA_SxM1AR . . . . . . . . . . . .
Page 1405 and 1406: HASH_SR . . . . . . . . . . . . . .
Page 1407 and 1408: RNG_DR . . . . . . . . . . . . . .
Page 1409 and 1410: Revision history RM0090 Revision hi
Page 1411 and 1412: Revision history RM0090 Table 238.
Page 1413 and 1414: Revision history RM0090 Table 238.
Page 1415 and 1416:
Revision history RM0090 Table 238.
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RM0090: Reference manual - STMicroelectronics

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