RM0090: Reference manual - STMicroelectronics

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<strong>RM0090</strong> USB on-the-go high-speed (OTG_HS) Table 182. OTG_HS register map and reset values (continued) Offset Register 31 0x568 0x584 0x588 0x5A4 0x5A8 0x5C4 0x5C8 0x5E4 0x5E8 0x604 0x608 0x624 OTG_HS_HCIN T3 Reserved Reset value 0 0 0 0 0 0 0 0 0 0 0 OTG_HS_HCS PLT4 SPLITEN Reserved COMPLSPLT XACTPOS DTERR FRMOR BBERR TXERR NYET ACK Doc ID 018909 Rev 3 1248/1416 NAK STALL AHBERR HUBADDR PRTADDR Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OTG_HS_HCIN T4 Reserved Reset value 0 0 0 0 0 0 0 0 0 0 0 OTG_HS_HCS PLT5 SPLITEN Reserved COMPLSPLT XACTPOS DTERR FRMOR BBERR TXERR NYET ACK NAK STALL AHBERR HUBADDR PRTADDR Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OTG_HS_HCIN T5 Reserved Reset value 0 0 0 0 0 0 0 0 0 0 0 OTG_HS_HCS PLT6 SPLITEN Reserved COMPLSPLT XACTPOS DTERR FRMOR BBERR TXERR NYET ACK NAK STALL AHBERR HUBADDR PRTADDR Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OTG_HS_HCIN T6 Reserved Reset value 0 0 0 0 0 0 0 0 0 0 0 OTG_HS_HCS PLT7 SPLITEN Reserved COMPLSPLT XACTPOS DTERR FRMOR BBERR TXERR NYET ACK NAK STALL AHBERR HUBADDR PRTADDR Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OTG_HS_HCIN T7 Reserved Reset value 0 0 0 0 0 0 0 0 0 0 0 OTG_HS_HCS PLT8 SPLITEN Reserved COMPLSPLT XACTPOS DTERR FRMOR BBERR TXERR NYET ACK NAK STALL AHBERR HUBADDR PRTADDR Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OTG_HS_HCIN T8 Reserved Reset value 0 0 0 0 0 0 0 0 0 0 0 OTG_HS_HCS PLT9 SPLITEN 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved COMPLSPLT XACTPOS DTERR FRMOR BBERR TXERR NYET ACK NAK STALL AHBERR HUBADDR PRTADDR Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CHH XFRC CHH XFRC CHH XFRC CHH XFRC CHH XFRC CHH XFRC
USB on-the-go high-speed (OTG_HS) <strong>RM0090</strong> Table 182. OTG_HS register map and reset values (continued) Offset Register 31 0x628 0x644 0x648 0x664 0x668 0x50C 0x52C 0x54C 0x56C 0x58C 0x5AC 0x5CC 0x5EC OTG_HS_HCIN T9 Reserved Reset value 0 0 0 0 0 0 0 0 0 0 0 OTG_HS_HCS PLT10 SPLITEN Reserved 1249/1416 Doc ID 018909 Rev 3 COMPLSPLT XACTPOS DTERR FRMOR BBERR TXERR NYET ACK NAK STALL AHBERR HUBADDR PRTADDR Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OTG_HS_HCIN T10 Reserved Reset value 0 0 0 0 0 0 0 0 0 0 0 OTG_HS_HCS PLT11 SPLITEN 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved COMPLSPLT XACTPOS DTERR FRMOR BBERR TXERR NYET ACK NAK STALL AHBERR HUBADDR PRTADDR Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OTG_HS_HCIN T11 Reserved Reset value 0 0 0 0 0 0 0 0 0 0 0 OTG_HS_HCIN TMSK0 Reserved DTERR FRMOR DTERRM FRMORM BBERR TXERR BBERRM TXERRM NYET ACK NAK NYET ACKM NAKM STALLM Reset value 0 0 0 0 0 0 0 0 0 0 0 OTG_HS_HCIN TMSK1 Reserved Reset value 0 0 0 0 0 0 0 0 0 0 0 OTG_HS_HCIN TMSK2 Reserved Reset value 0 0 0 0 0 0 0 0 0 0 0 OTG_HS_HCIN TMSK3 Reserved Reset value 0 0 0 0 0 0 0 0 0 0 0 OTG_HS_HCIN TMSK4 Reserved Reset value 0 0 0 0 0 0 0 0 0 0 0 OTG_HS_HCIN TMSK5 Reserved Reset value 0 0 0 0 0 0 0 0 0 0 0 OTG_HS_HCIN TMSK6 Reserved Reset value 0 0 0 0 0 0 0 0 0 0 0 OTG_HS_HCIN TMSK7 Reserved Reset value 0 0 0 0 0 0 0 0 0 0 0 DTERRM FRMORM DTERRM FRMORM DTERRM FRMORM DTERRM FRMORM DTERRM FRMORM DTERRM FRMORM DTERRM FRMORM BBERRM TXERRM BBERRM TXERRM BBERRM TXERRM BBERRM TXERRM BBERRM TXERRM BBERRM TXERRM BBERRM TXERRM NYET ACKM NYET ACKM NYET ACKM NYET ACKM NYET ACKM NYET ACKM NYET ACKM NAKM STALLM NAKM STALLM NAKM STALLM NAKM STALLM NAKM STALLM NAKM STALLM NAKM STALLM STALL AHBERR AHBERR CHHM AHBERR CHHM AHBERR CHHM AHBERR CHHM AHBERR CHHM AHBERR CHHM AHBERR CHHM CHH XFRC CHH XFRC CHH XFRC CHHM XFRCM XFRCM XFRCM XFRCM XFRCM XFRCM XFRCM XFRCM
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RM0090 Reference manual STM32F40x,
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Contents RM0090 3.5.3 Erase . . . .
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Contents RM0090 6.3.1 RCC clock con
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Contents RM0090 7.4.7 GPIO port bit
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Contents RM0090 10.3.4 Falling trig
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Contents RM0090 12.4.2 Independent
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Contents RM0090 14.3.3 Repetition c
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Contents RM0090 15.4.12 TIMx auto-r
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Contents RM0090 17.4.6 TIM6&TIM7 co
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Contents RM0090 22.1 HASH introduct
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Contents RM0090 24.3.3 Tx mailboxes
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Contents RM0090 26.3.14 Hardware fl
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Contents RM0090 28.4.13 SD I/O mode
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Contents RM0090 29.7 Ethernet inter
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Contents RM0090 31.3.1 High-speed O
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Contents RM0090 33.2 Reference ARM
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List of tables RM0090 List of table
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List of tables RM0090 Table 98. Tra
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List of tables RM0090 Table 192. NO
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List of figures RM0090 Figure 49. A
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List of figures RM0090 Figure 151.
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Documentation conventions RM0090 1
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Memory and bus architecture RM0090
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Embedded Flash memory interface RM0
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CRC calculation unit RM0090 4 CRC c
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CRC calculation unit RM0090 Bits 7:
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Power control (PWR) RM0090 Figure 7
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Power control (PWR) RM0090 When the
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Power control (PWR) RM0090 mode (se
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Power control (PWR) RM0090 A PVDO f
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Power control (PWR) RM0090 5.3.3 Sl
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Power control (PWR) RM0090 If an ac
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Power control (PWR) RM0090 I/O stat
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Power control (PWR) RM0090 Safe RTC
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Power control (PWR) RM0090 Bit 4 PV
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Power control (PWR) RM0090 5.4.3 PW
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DMA controller (DMA) RM0090 9 DMA c
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DMA controller (DMA) RM0090 9.3 DMA
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DMA controller (DMA) RM0090 Figure
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DMA controller (DMA) RM0090 Table 3
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DMA controller (DMA) RM0090 In dire
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DMA controller (DMA) RM0090 Figure
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DMA controller (DMA) RM0090 memory
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DMA controller (DMA) RM0090 9.3.11
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DMA controller (DMA) RM0090 9.4 DMA
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DMA controller (DMA) RM0090 Bits 25
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DMA controller (DMA) RM0090 9.5.5 D
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DMA controller (DMA) RM0090 15 14 1
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Interrupts and events RM0090 10 Int
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Interrupts and events RM0090 Table
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Interrupts and events RM0090 genera
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Interrupts and events RM0090 10.3 E
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Interrupts and events RM0090 15 14
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Basic timers (TIM6&TIM7) RM0090 17
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Basic timers (TIM6&TIM7) RM0090 Fig
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Basic timers (TIM6&TIM7) RM0090 17.
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Independent watchdog (IWDG) RM0090
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Window watchdog (WWDG) RM0090 19 Wi
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Window watchdog (WWDG) RM0090 case,
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Window watchdog (WWDG) RM0090 19.6
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Window watchdog (WWDG) RM0090 19.6.
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Random number generator (RNG) RM009
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Hash processor (HASH) RM0090 22.3 H
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Hash processor (HASH) RM0090 has le
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Hash processor (HASH) RM0090 The le
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Hash processor (HASH) RM0090 with v
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Hash processor (HASH) RM0090 Proced
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Hash processor (HASH) RM0090 Bit 12
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Hash processor (HASH) RM0090 22.4.2
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Hash processor (HASH) RM0090 Bit 3
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Hash processor (HASH) RM0090 Table
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Real-time clock (RTC) RM0090 23.2 R
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Real-time clock (RTC) RM0090 RTC_TR
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Real-time clock (RTC) RM0090 window
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Debug support (DBG) RM0090 33 Debug
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Debug support (DBG) RM0090 31 30 29
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Debug support (DBG) RM0090 Bit 20:1
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Device electronic signature RM0090
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A ADC_CCR . . . . . . . . . . . . .
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DMA_SxM1AR . . . . . . . . . . . .
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HASH_SR . . . . . . . . . . . . . .
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RNG_DR . . . . . . . . . . . . . .
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Revision history RM0090 Revision hi
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Revision history RM0090 Table 238.
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RM0090: Reference manual - STMicroelectronics

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