RM0090: Reference manual - STMicroelectronics

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<strong>RM0090</strong> Debug support (DBG) 33.17.10 Example of configuration ● Set the bit TRCENA in the Debug Exception and Monitor Control Register (DEMCR) ● Write the TPIU Current Port Size Register to the desired value (default is 0x1 for a 1-bit port size) ● Write TPIU Formatter and Flush Control Register to 0x102 (default value) ● Write the TPIU Select Pin Protocol to select the sync or async mode. Example: 0x2 for async NRZ mode (UART like) ● Write the DBGMCU control register to 0x20 (bit IO_TRACEN) to assign TRACE I/Os for async mode. A TPIU Sync packet is emitted at this time (FF_FF_FF_7F) ● Configure the ITM and write the ITM Stimulus register to output a value 33.18 DBG register map The following table summarizes the Debug registers . Table 237. DBG register map and reset values Addr. Register 31 0xE004 2000 0xE004 2004 0xE004 2008 0xE004 200C DBGMCU_IDC ODE 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 REV_ID Reserved DEV_ID Reset value (1) X X X X X X X X X X X X X X X X X X X X X X X X X X X X DBGMCU_CR Reserved DBG_TIM7_STOP DBG_TIM6_STOP DBG_TIM5_STOP DBG_TIM8_STOP DBG_I2C2_SMBUS_TIMEOUT Reserved TRAC E_ MODE [1:0] Doc ID 018909 Rev 3 1398/1416 TR AC E_ IO E N Reserved DBG_STANDBY DBG_STOP DBG_SLEEP Reset value 0 0 0 0 0 0 0 0 0 0 0 DBGMCU_ APB1_FZ Reserved DBG_CAN2_STOP DBG_CAN1_STOP Reserved DBG_I2C3_SMBUS_TIMEOUT DBG_I2C2_SMBUS_TIMEOUT DBG_I2C1_SMBUS_TIMEOUT Reserved Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DBGMCU_ APB2_FZ Reserved DBG_TIM11_STOP DBG_TIM10_STOP DBG_TIM9_STOP DBG_IWDG_STOP DBG_WWDG_STOP Reserved DBG_RTC_STOP DBG_TIM14_STOP Reserved Reset value 0 0 0 0 0 1. The reset value is product dependent. For more information, refer to Section 33.6.1: MCU device ID code. DBG_TIM13_STOP DBG_TIM12_STOP DBG_TIM7_STOP DBG_TIM6_STOP DBG_TIM5_STOP DBG_TIM4_STOP DBG_TIM3_STOP DBG_TIM2_STOP DBG_TIM8_STOP DBG_TIM1_STOP
Device electronic signature <strong>RM0090</strong> 34 Device electronic signature The electronic signature is stored in the Flash memory area. It can be read using the JTAG/SWD or the CPU. It contains factory-programmed identification data that allow the user firmware or other external devices to automatically match its interface to the characteristics of the STM32F4xx microcontrollers. 34.1 Unique device ID register (96 bits) The unique device identifier is ideally suited: ● for use as serial numbers (for example USB string serial numbers or other end applications) ● for use as security keys in order to increase the security of code in Flash memory while using and combining this unique ID with software cryptographic primitives and protocols before programming the internal Flash memory ● to activate secure boot processes, etc. The 96-bit unique device identifier provides a reference number which is unique for any device and in any context. These bits can never be altered by the user. The 96-bit unique device identifier can also be read in single bytes/half-words/words in different ways and then be concatenated using a custom algorithm. Base address: 0x1FFF 7A10 Address offset: 0x00 Read only = 0xXXXX XXXX where X is factory-programmed 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 U_ID(31:0) r r r r r r r r r r r r r r r r r r r r r r r r r r r r r r r r Bits 31:0 U_ID(31:0): 31:0 unique ID bits Address offset: 0x04 Read only = 0xXXXX XXXX where X is factory-programmed 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 U_ID(63:48) r r r r r r r r r r r r r r r r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 U_ID(47:32) r r r r r r r r r r r r r r r r Bits 31:0 U_ID(63:32): 63:32 unique ID bits 1399/1416 Doc ID 018909 Rev 3
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RM0090 Reference manual STM32F40x,
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Contents RM0090 3.5.3 Erase . . . .
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Contents RM0090 6.3.1 RCC clock con
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Contents RM0090 7.4.7 GPIO port bit
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Contents RM0090 10.3.4 Falling trig
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Contents RM0090 12.4.2 Independent
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Contents RM0090 14.3.3 Repetition c
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Contents RM0090 15.4.12 TIMx auto-r
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Contents RM0090 17.4.6 TIM6&TIM7 co
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Contents RM0090 22.1 HASH introduct
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Contents RM0090 24.3.3 Tx mailboxes
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Contents RM0090 26.3.14 Hardware fl
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Contents RM0090 28.4.13 SD I/O mode
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Contents RM0090 29.7 Ethernet inter
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Contents RM0090 31.3.1 High-speed O
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Contents RM0090 33.2 Reference ARM
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List of tables RM0090 List of table
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List of tables RM0090 Table 98. Tra
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List of tables RM0090 Table 192. NO
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List of figures RM0090 Figure 49. A
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List of figures RM0090 Figure 151.
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Documentation conventions RM0090 1
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Memory and bus architecture RM0090
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Embedded Flash memory interface RM0
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CRC calculation unit RM0090 4 CRC c
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CRC calculation unit RM0090 Bits 7:
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Power control (PWR) RM0090 Figure 7
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Power control (PWR) RM0090 When the
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Power control (PWR) RM0090 mode (se
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Power control (PWR) RM0090 A PVDO f
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Power control (PWR) RM0090 5.3.3 Sl
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Power control (PWR) RM0090 If an ac
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Power control (PWR) RM0090 I/O stat
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Power control (PWR) RM0090 Safe RTC
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Power control (PWR) RM0090 Bit 4 PV
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Power control (PWR) RM0090 5.4.3 PW
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DMA controller (DMA) RM0090 9 DMA c
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DMA controller (DMA) RM0090 9.3 DMA
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DMA controller (DMA) RM0090 Figure
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DMA controller (DMA) RM0090 Table 3
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DMA controller (DMA) RM0090 In dire
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DMA controller (DMA) RM0090 Figure
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DMA controller (DMA) RM0090 memory
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DMA controller (DMA) RM0090 9.3.11
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DMA controller (DMA) RM0090 9.4 DMA
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DMA controller (DMA) RM0090 Bits 25
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DMA controller (DMA) RM0090 9.5.5 D
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Interrupts and events RM0090 Table
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Interrupts and events RM0090 genera
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Interrupts and events RM0090 10.3 E
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Basic timers (TIM6&TIM7) RM0090 17
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Basic timers (TIM6&TIM7) RM0090 Fig
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Basic timers (TIM6&TIM7) RM0090 17.
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Independent watchdog (IWDG) RM0090
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Independent watchdog (IWDG) RM0090
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Window watchdog (WWDG) RM0090 19 Wi
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Window watchdog (WWDG) RM0090 case,
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Window watchdog (WWDG) RM0090 19.6
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Window watchdog (WWDG) RM0090 19.6.
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Hash processor (HASH) RM0090 22.3 H
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Hash processor (HASH) RM0090 has le
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Hash processor (HASH) RM0090 with v
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Hash processor (HASH) RM0090 Proced
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Hash processor (HASH) RM0090 Bit 12
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Hash processor (HASH) RM0090 22.4.2
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Hash processor (HASH) RM0090 Bit 3
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Real-time clock (RTC) RM0090 23.2 R
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Real-time clock (RTC) RM0090 RTC_TR
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Page 1391 and 1392: Debug support (DBG) RM0090 Bit 20:1
Page 1397: Debug support (DBG) RM0090 33.17.9
Page 1401 and 1402: A ADC_CCR . . . . . . . . . . . . .
Page 1403 and 1404: DMA_SxM1AR . . . . . . . . . . . .
Page 1405 and 1406: HASH_SR . . . . . . . . . . . . . .
Page 1407 and 1408: RNG_DR . . . . . . . . . . . . . .
Page 1409 and 1410: Revision history RM0090 Revision hi
Page 1411 and 1412: Revision history RM0090 Table 238.
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RM0090: Reference manual - STMicroelectronics

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