RM0090: Reference manual - STMicroelectronics

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<strong>RM0090</strong> General-purpose timers (TIM2 to TIM5) 15.4.20 TIM5 option register (TIM5_OR) Address offset: 0x50 Reset value: 0x0000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TI4_RMP Reserved rw rw Reserved Bits 15:8 Reserved, must be kept at reset value. Bits 7:6 TI4_RMP: Timer Input 4 remap Set and cleared by software. 00: TIM5 Channel4 is connected to the GPIO: Refer to the Alternate function mapping table in the datasheets. 01: the LSI internal clock is connected to the TIM5_CH4 input for calibration purposes 10: the LSE internal clock is connected to the TIM5_CH4 input for calibration purposes 11: the RTC wakeup interrupt is connected to TIM5_CH4 input for calibration purposes. Wakeup interrupt should be enabled. Bits 5:0 Reserved, must be kept at reset value. 15.4.21 TIMx register map TIMx registers are mapped as described in the table below: 31 Table 76. TIM2 to TIM5 register map and reset values Offset Register 0x00 0x04 0x08 0x0C 0x10 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DIR TIMx_CR1 Reserved CKD [1:0] CMS [1:0] Reset value 0 0 0 0 0 0 0 0 0 0 TI1S TIMx_CR2 Reserved MMS[2:0] Reserved Reset value 0 0 0 0 0 ETP TIMx_SMCR Reserved ETPS [1:0] ETF[3:0] TS[2:0] SMS[2:0] Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TIMx_DIER ECE Reserved TDE Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 TIMx_SR Reserved Reset value 0 0 0 0 0 0 0 0 0 0 TG 0x14 TIMx_EGR Reserved Reset value 0 0 0 0 0 0 TIMx_CCMR1 Output Compare mode Reserved OC2M [2:0] CC2S [1:0] OC1M [2:0] CC1S [1:0] 0x18 Reset value TIMx_CCMR1 Input Capture mode Reserved 0 0 0 0 IC2F[3:0] 0 0 IC2 PSC [1:0] 0 0 CC2S [1:0] 0 0 0 0 IC1F[3:0] 0 0 IC1 PSC [1:0] 0 0 CC1S [1:0] Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OC2CE COMDE CC4DE CC4OF CC3OF CC3DE CC2DE OC2PE OC2FE CC2OF CC1OF CC1DE UDE Doc ID 018909 Rev 3 476/1416 Reserved ARPE MSM Reserved TIE OC1CE TIF Reserved CC4IE Reserved CC4IF Reserved CC4G OPM URS CCDS Reserved CC3IE CC2IE CC3IF CC2IF CC3G CC2G OC1PE OC1FE UDIS CEN CC1IE UIE CC1IF UIF CC1G UG
General-purpose timers (TIM2 to TIM5) <strong>RM0090</strong> 31 Table 76. TIM2 to TIM5 register map and reset values (continued) Offset Register 0x1C 0x20 0x24 0x28 0x2C TIMx_CCMR2 Output Compare mode Reserved Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TIMx_CCMR2 Input Capture mode Reserved Refer to Table 2 on page 53 for the register boundary addresses. 477/1416 Doc ID 018909 Rev 3 O24CE OC4M [2:0] IC4F[3:0] OC4PE OC4FE IC4 PSC [1:0] CC4S [1:0] CC4S [1:0] OC3CE OC3M [2:0] IC3F[3:0] OC3PE OC3FE IC3 PSC [1:0] Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TIMx_CCER Reserved CC4NP Reserved CC4P CC4E CC3NP Reserved CC3P CC3E CC2NP Reserved CC3S [1:0] CC3S [1:0] CC2P CC2E CC1NP Reserved CC1P CC1E Reset value 0 0 0 0 0 0 0 0 0 0 0 0 TIMx_CNT CNT[31:16] (TIM2 and TIM5 only, reserved on the other timers) CNT[15:0] Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TIMx_PSC Reserved PSC[15:0] Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TIMx_ARR ARR[31:16] (TIM2 and TIM5 only, reserved on the other timers) ARR[15:0] Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x30 Reserved 0x34 0x38 0x3C 0x40 TIMx_CCR1 CCR1[31:16] (TIM2 and TIM5 only, reserved on the other timers) CCR1[15:0] Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TIMx_CCR2 CCR2[31:16] (TIM2 and TIM5 only, reserved on the other timers) CCR2[15:0] Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TIMx_CCR3 CCR3[31:16] (TIM2 and TIM5 only, reserved on the other timers) CCR3[15:0] Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TIMx_CCR4 CCR4[31:16] (TIM2 and TIM5 only, reserved on the other timers) CCR4[15:0] Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x44 Reserved 0x48 0x4C 0x50 0x50 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TIMx_DCR Reserved DBL[4:0] Reserved DBA[4:0] Reset value 0 0 0 0 0 0 0 0 0 0 TIMx_DMAR Reserved DMAB[15:0] Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TIM2_OR Reserved Reserved ITR1_ RMP Reserved Reset value 0 0 TIM5_OR Reserved Reserved IT4_R MP Reserved Reset value 0 0
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RM0090 Reference manual STM32F40x,
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Contents RM0090 3.5.3 Erase . . . .
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Contents RM0090 6.3.1 RCC clock con
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Contents RM0090 7.4.7 GPIO port bit
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Contents RM0090 10.3.4 Falling trig
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Contents RM0090 12.4.2 Independent
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Contents RM0090 14.3.3 Repetition c
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Contents RM0090 15.4.12 TIMx auto-r
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Contents RM0090 17.4.6 TIM6&TIM7 co
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Contents RM0090 22.1 HASH introduct
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Contents RM0090 24.3.3 Tx mailboxes
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Contents RM0090 26.3.14 Hardware fl
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Contents RM0090 28.4.13 SD I/O mode
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Contents RM0090 29.7 Ethernet inter
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Contents RM0090 31.3.1 High-speed O
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Contents RM0090 33.2 Reference ARM
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List of tables RM0090 List of table
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List of tables RM0090 Table 98. Tra
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List of tables RM0090 Table 192. NO
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List of figures RM0090 Figure 49. A
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List of figures RM0090 Figure 151.
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Documentation conventions RM0090 1
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Memory and bus architecture RM0090
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Embedded Flash memory interface RM0
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CRC calculation unit RM0090 4 CRC c
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CRC calculation unit RM0090 Bits 7:
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Power control (PWR) RM0090 Figure 7
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Power control (PWR) RM0090 When the
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Power control (PWR) RM0090 mode (se
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Power control (PWR) RM0090 A PVDO f
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Power control (PWR) RM0090 5.3.3 Sl
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Power control (PWR) RM0090 If an ac
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Power control (PWR) RM0090 I/O stat
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Power control (PWR) RM0090 Safe RTC
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Power control (PWR) RM0090 Bit 4 PV
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Power control (PWR) RM0090 5.4.3 PW
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DMA controller (DMA) RM0090 9 DMA c
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DMA controller (DMA) RM0090 9.3 DMA
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DMA controller (DMA) RM0090 Figure
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DMA controller (DMA) RM0090 Table 3
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DMA controller (DMA) RM0090 In dire
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DMA controller (DMA) RM0090 Figure
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DMA controller (DMA) RM0090 memory
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DMA controller (DMA) RM0090 9.3.11
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DMA controller (DMA) RM0090 9.4 DMA
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DMA controller (DMA) RM0090 Bits 25
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DMA controller (DMA) RM0090 9.5.5 D
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DMA controller (DMA) RM0090 Bits 8
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DMA controller (DMA) RM0090 15 14 1
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Interrupts and events RM0090 10 Int
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Interrupts and events RM0090 Table
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Interrupts and events RM0090 genera
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Interrupts and events RM0090 10.3 E
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Interrupts and events RM0090 15 14
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Independent watchdog (IWDG) RM0090
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Window watchdog (WWDG) RM0090 19 Wi
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Window watchdog (WWDG) RM0090 case,
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Window watchdog (WWDG) RM0090 19.6
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Window watchdog (WWDG) RM0090 19.6.
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Random number generator (RNG) RM009
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Hash processor (HASH) RM0090 22.3 H
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Hash processor (HASH) RM0090 has le
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Hash processor (HASH) RM0090 The le
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Hash processor (HASH) RM0090 with v
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Hash processor (HASH) RM0090 Proced
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Hash processor (HASH) RM0090 Bit 12
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Hash processor (HASH) RM0090 22.4.2
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Hash processor (HASH) RM0090 Bit 3
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Hash processor (HASH) RM0090 HASH_H
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Hash processor (HASH) RM0090 Table
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Real-time clock (RTC) RM0090 23.2 R
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Real-time clock (RTC) RM0090 The as
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Real-time clock (RTC) RM0090 23.3.5
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Real-time clock (RTC) RM0090 RTC_TR
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Real-time clock (RTC) RM0090 window
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Debug support (DBG) RM0090 33 Debug
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Debug support (DBG) RM0090 33.4.3 I
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Debug support (DBG) RM0090 Figure 4
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Debug support (DBG) RM0090 Only the
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Debug support (DBG) RM0090 Table 22
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Debug support (DBG) RM0090 Note: No
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Debug support (DBG) RM0090 33.9 AHB
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Debug support (DBG) RM0090 33.11 Ca
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Debug support (DBG) RM0090 For this
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Debug support (DBG) RM0090 33.15.3
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Debug support (DBG) RM0090 31 30 29
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Debug support (DBG) RM0090 Bit 20:1
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Device electronic signature RM0090
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A ADC_CCR . . . . . . . . . . . . .
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DMA_SxM1AR . . . . . . . . . . . .
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HASH_SR . . . . . . . . . . . . . .
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RNG_DR . . . . . . . . . . . . . .
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Revision history RM0090 Revision hi
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Revision history RM0090 Table 238.
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show all

RM0090: Reference manual - STMicroelectronics

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