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RM0090: Reference manual - STMicroelectronics

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USB on-the-go full-speed (OTG_FS) <strong>RM0090</strong><br />

OTG_FS USB configuration register (OTG_FS_GUSBCFG)<br />

Address offset: 0x00C<br />

Reset value: 0x0000 0A00<br />

This register can be used to configure the core after power-on or a changing to host mode or<br />

device mode. It contains USB and USB-PHY related configuration parameters. The<br />

application must program this register before starting any transactions on either the AHB or<br />

the USB. Do not make changes to this register after the initial programming.<br />

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0<br />

CTXPKT<br />

FDMOD<br />

FHMOD<br />

Reserved<br />

rw rw rw rw<br />

1051/1416 Doc ID 018909 Rev 3<br />

TRDT<br />

r/rw HNPCAP<br />

SRPCAP<br />

r/rw<br />

Res.<br />

PHYSEL<br />

Reserved<br />

TOCAL<br />

wo rw<br />

Bits 31:20 Reserved, must be kept at reset value.<br />

Bit 31 CTXPKT: Corrupt Tx packet<br />

This bit is for debug purposes only. Never set this bit to 1.<br />

Note: Accessible in both device and host modes.<br />

Bit 30 FDMOD: Force device mode<br />

Writing a 1 to this bit forces the core to device mode irrespective of the OTG_FS_ID input pin.<br />

0: Normal mode<br />

1: Force device mode<br />

After setting the force bit, the application must wait at least 25 ms before the change takes<br />

effect.<br />

Note: Accessible in both device and host modes.<br />

Bit 29 FHMOD: Force host mode<br />

Writing a 1 to this bit forces the core to host mode irrespective of the OTG_FS_ID input pin.<br />

0: Normal mode<br />

1: Force host mode<br />

After setting the force bit, the application must wait at least 25 ms before the change takes<br />

effect.<br />

Note: Accessible in both device and host modes.<br />

Bits 28:14 Reserved, must be kept at reset value.<br />

Bits 13:10 TRDT: USB turnaround time<br />

Sets the turnaround time in PHY clocks.<br />

To calculate the value of TRDT, use the following formula:<br />

TRDT = 4 × AHB clock + 1 PHY clock<br />

Examples:<br />

1. if AHB clock = 72 MHz (PHY Clock is 48), the TRDT is set to 9.<br />

2. if AHB clock = 48 MHz (PHY Clock is 48), the TRDT is set to 5.<br />

Note: Only accessible in device mode.<br />

Bit 9 HNPCAP: HNP-capable<br />

The application uses this bit to control the OTG_FS controller’s HNP capabilities.<br />

0: HNP capability is not enabled.<br />

1: HNP capability is enabled.<br />

Note: Accessible in both device and host modes.

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