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RM0090: Reference manual - STMicroelectronics

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<strong>RM0090</strong> USB on-the-go high-speed (OTG_HS)<br />

OTG_HS general core configuration register (OTG_HS_GCCFG)<br />

Address offset: 0x038<br />

Reset value: 0x0000 0000<br />

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0<br />

Reserved<br />

NOVBUSSENS<br />

SOFOUTEN<br />

VBUSBSEN<br />

VBUSASEN<br />

I2CPADEN<br />

.PWRDWN<br />

rw rw rw rw rw rw<br />

Reserved<br />

Bits 31:22 Reserved, must be kept at reset value.<br />

Bit 21 NOVBUSSENS: VBUS sensing disable option<br />

When this bit is set, VBUS is considered internally to be always at VBUS valid level (5 V). This<br />

option removes the need for a dedicated VBUS pad, and leave this pad free to be used for<br />

other purposes such as a shared functionality. VBUS connection can be remapped on<br />

another general purpose input pad and monitored by software.<br />

This option is only suitable for host-only or device-only applications.<br />

0: VBUS sensing available by hardware<br />

1: VBUS sensing not available by hardware.<br />

Bit 20 SOFOUTEN: SOF output enable<br />

0: SOF pulse not available on PAD<br />

1: SOF pulse available on PAD<br />

Bit 19 VBUSBSEN: Enable the V BUS sensing “B” device<br />

0: V BUS sensing “B” disabled<br />

1: V BUS sensing “B” enabled<br />

Bit 18 VBUSASEN: Enable the V BUS sensing “A” device<br />

0: V BUS sensing “A” disabled<br />

1: V BUS sensing “A” enabled<br />

Bit 17 I2CPADEN: Enable I 2 C bus connection for the external I 2 C PHY interface.<br />

0: I 2 C bus disabled<br />

1: I 2 C bus enabled<br />

Bit 16 PWRDWN: Power down<br />

Used to activate the transceiver in transmission/reception<br />

0: Power down active<br />

1: Power down deactivated (“Transceiver active”)<br />

Bits 15:0 Reserved, must be kept at reset value.<br />

Doc ID 018909 Rev 3 1202/1416

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