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RM0090: Reference manual - STMicroelectronics

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<strong>RM0090</strong> USB on-the-go high-speed (OTG_HS)<br />

Bit 2 PENA: Port enable<br />

A port is enabled only by the core after a reset sequence, and is disabled by an overcurrent<br />

condition, a disconnect condition, or by the application clearing this bit. The application<br />

cannot set this bit by a register write. It can only clear it to disable the port. This bit does not<br />

trigger any interrupt to the application.<br />

0: Port disabled<br />

1: Port enabled<br />

Bit 1 PCDET: Port connect detected<br />

The core sets this bit when a device connection is detected to trigger an interrupt to the<br />

application using the host port interrupt bit in the Core interrupt register (HPRTINT bit in<br />

OTG_HS_GINTSTS). The application must write a 1 to this bit to clear the interrupt.<br />

Bit 0 PCSTS: Port connect status<br />

0: No device is attached to the port<br />

1: A device is attached to the port<br />

OTG_HS host channel-x characteristics register (OTG_HS_HCCHARx)<br />

(x = 0..11, where x = Channel_number)<br />

Address offset: 0x500 + (Channel_number × 0x20)<br />

Reset value: 0x0000 0000<br />

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0<br />

CHENA<br />

CHDIS<br />

ODDFRM<br />

DAD MC<br />

EPTYP<br />

LSDEV<br />

Reserved<br />

EPDIR<br />

EPNUM MPSIZ<br />

rs rs rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw<br />

Bit 31 CHENA: Channel enable<br />

This field is set by the application and cleared by the OTG host.<br />

0: Channel disabled<br />

1: Channel enabled<br />

Bit 30 CHDIS: Channel disable<br />

The application sets this bit to stop transmitting/receiving data on a channel, even before the<br />

transfer for that channel is complete. The application must wait for the Channel disabled<br />

interrupt before treating the channel as disabled.<br />

Bit 29 ODDFRM: Odd frame<br />

This field is set (reset) by the application to indicate that the OTG host must perform a<br />

transfer in an odd frame. This field is applicable for only periodic (isochronous and interrupt)<br />

transactions.<br />

0: Even (micro) frame<br />

1: Odd (micro) frame<br />

Bits 28:22 DAD: Device address<br />

This field selects the specific device serving as the data source or sink.<br />

Doc ID 018909 Rev 3 1210/1416

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