RM0090: Reference manual - STMicroelectronics

RM0090 Analog-to-digital converter (ADC)
Figure 41. Multi ADC block diagram (1)
ADCx_IN0
ADCx_IN1
ADCx_IN15
EXTI_11
EXTI_15
GPIO
Ports
Temp. sensor
VREFINT VBAT Start trigger mux
(regular group)
Start trigger mux
(injected group)
Regular
channels
Regular
channels
Regular
channels
Injected
channels
Injected
channels
internal triggers
Injected
channels
1. Although external triggers are present on ADC2 and ADC3 they are not shown in this diagram.
2. In the Dual ADC mode, the ADC3 slave part is not present.
Regular data register
(16 (12 bits)
Dual/Triple
mode control
Injected data registers
(4 x 16 bits)
ADC3 (2) (Slave)
Regular data register
(12 (16 bits) bits)
Injected data registers
(4 x 16 bits)
Common regular data register
(32 bits) (3)
Regular data register
(16 bits)
ADC2 (Slave)
Common part
Injected data registers
(4 x 16 bits)
ADC1 (Master)
3. In Triple ADC mode, the ADC common data register (ADC_CDR) contains the ADC1, ADC2 and ADC3’s
regular converted data. All 32 register bits are used according to a selected storage order.
In Dual ADC mode, the ADC common data register (ADC_CDR) contains both the ADC1 and ADC2’s
regular converted data. All 32 register bits are used.
Doc ID 018909 Rev 3 276/1416
Address/data bus
ai16053