RM0090: Reference manual - STMicroelectronics

Window watchdog (WWDG) RM0090
case, the corresponding interrupt service routine (ISR) should reload the WWDG counter to
avoid the WWDG reset, then trigger the required actions.
The EWI interrupt is cleared by writing '0' to the EWIF bit in the WWDG_SR register.
Note: When the EWI interrupt cannot be served, e.g. due to a system lock in a higher priority task,
the WWDG reset will eventually be generated.
19.4 How to program the watchdog timeout
You can use the formula in Figure 200 to calculate the WWDG timeout.
Warning: When writing to the WWDG_CR register, always write 1 in the
T6 bit to avoid generating an immediate reset.
Figure 200. Window watchdog timing diagram
The formula to calculate the timeout value is given by:
× 2 WDGTB
= × × ( t[ 5:0]
+ 1)
( ms)
where:
T[6:0] CNT downcounter
W[6:0]
0x3F
T6 bit
RESET
t WWDG: WWDG timeout
Refresh not allowed
t WWDG t PCLK1 4096
t PCLK1: APB1 clock period measured in ms
Refresh allowed
Refer to the table below for the minimum and maximum values of the T WWDG.
539/1416 Doc ID 018909 Rev 3
Time
ai17101b