RM0090: Reference manual - STMicroelectronics

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<strong>RM0090</strong> Serial peripheral interface (SPI) Bit 2:1 DATLEN: Data length to be transferred 00: 16-bit data length 01: 24-bit data length 10: 32-bit data length 11: Not allowed Note: For correct operation, these bits should be configured when the I 2 S is disabled. Not used in SPI mode. Bit 0 CHLEN: Channel length (number of bits per audio channel) 0: 16-bit wide 1: 32-bit wide The bit write operation has a meaning only if DATLEN = 00 otherwise the channel length is fixed to 32-bit by hardware whatever the value filled in. Not used in SPI mode. Note: For correct operation, this bit should be configured when the I 2 S is disabled. 27.5.9 SPI_I 2 S prescaler register (SPI_I2SPR) Address offset: 0x20 Reset value: 0000 0010 (0x0002) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved Bits 15:10 Reserved, must be kept at reset value. MCKOE ODD I2SDIV rw rw rw Bit 9 MCKOE: Master clock output enable 0: Master clock output is disabled 1: Master clock output is enabled Note: This bit should be configured when the I 2 S is disabled. It is used only when the I 2 S is in master mode. Not used in SPI mode. Bit 8 ODD: Odd factor for the prescaler 0: real divider value is = I2SDIV *2 1: real divider value is = (I2SDIV * 2)+1 Refer to Section 27.4.4 on page 824. Not used in SPI mode. Note: This bit should be configured when the I 2 S is disabled. It is used only when the I 2 S is in master mode. Bit 7:0 I2SDIV: I2S Linear prescaler I2SDIV [7:0] = 0 or I2SDIV [7:0] = 1 are forbidden values. Refer to Section 27.4.4 on page 824. Not used in SPI mode. Note: These bits should be configured when the I 2 S is disabled. It is used only when the I 2 S is in master mode. Doc ID 018909 Rev 3 840/1416
Serial peripheral interface (SPI) <strong>RM0090</strong> 27.5.10 SPI register map The table provides shows the SPI register map and reset values. Table 125. SPI register map and reset values Offset Register 31 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 SPI_CR1 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved Refer to Table 2 on page 53 for the register boundary addresses. 841/1416 Doc ID 018909 Rev 3 BIDIMODE BIDIOE CRCEN CRCNEXT DFF RXONLY SSM SSI LSBFIRST SPE BR [2:0] Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SPI_CR2 Reserved MSTR CPOL CPHA TXEIE RXNEIE ERRIE FRF Reserved SSOE TXDMAEN RXDMAEN Reset value 0 0 0 0 0 0 0 SPI_SR Reserved FRE BSY OVR MODF CRCERR UDR CHSIDE TXE RXNE Reset value 0 0 0 0 0 0 0 1 0 SPI_DR Reset value Reserved 0 0 0 0 0 0 DR[15:0] 0 0 0 0 0 0 0 0 0 0 SPI_CRCPR Reset value Reserved 0 0 0 0 0 CRCPOLY[15:0] 0 0 0 0 0 0 0 0 1 1 1 SPI_RXCRCR Reset value Reserved 0 0 0 0 0 0 RxCRC[15:0] 0 0 0 0 0 0 0 0 0 0 SPI_TXCRCR Reset value Reserved 0 0 0 0 0 0 TxCRC[15:0] 0 0 0 0 0 0 0 0 0 0 SPI_I2SCFGR Reserved Reset value 0 0 0 0 0 0 0 0 0 0 0 SPI_I2SPR Reserved I2SMOD I2SE I2SCFG MCKOE ODD PCMSYNC Reserved I2SSTD CKPOL I2SDIV Reset value 0 0 0 0 0 0 0 0 1 0 DATLEN CHLEN
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RM0090 Reference manual STM32F40x,
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Contents RM0090 3.5.3 Erase . . . .
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Contents RM0090 6.3.1 RCC clock con
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Contents RM0090 12.4.2 Independent
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Contents RM0090 31.3.1 High-speed O
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Contents RM0090 33.2 Reference ARM
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List of tables RM0090 List of table
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List of tables RM0090 Table 98. Tra
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List of tables RM0090 Table 192. NO
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List of figures RM0090 Figure 49. A
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List of figures RM0090 Figure 151.
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Documentation conventions RM0090 1
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Memory and bus architecture RM0090
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Embedded Flash memory interface RM0
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CRC calculation unit RM0090 4 CRC c
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CRC calculation unit RM0090 Bits 7:
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Power control (PWR) RM0090 Figure 7
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Power control (PWR) RM0090 When the
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Power control (PWR) RM0090 mode (se
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Power control (PWR) RM0090 A PVDO f
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Power control (PWR) RM0090 5.3.3 Sl
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Power control (PWR) RM0090 I/O stat
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Power control (PWR) RM0090 Safe RTC
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DMA controller (DMA) RM0090 9 DMA c
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DMA controller (DMA) RM0090 9.3 DMA
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DMA controller (DMA) RM0090 Figure
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DMA controller (DMA) RM0090 Table 3
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DMA controller (DMA) RM0090 In dire
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DMA controller (DMA) RM0090 memory
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DMA controller (DMA) RM0090 9.3.11
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DMA controller (DMA) RM0090 9.4 DMA
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DMA controller (DMA) RM0090 15 14 1
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Window watchdog (WWDG) RM0090 19.6.
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Hash processor (HASH) RM0090 has le
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Hash processor (HASH) RM0090 The le
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Hash processor (HASH) RM0090 with v
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Hash processor (HASH) RM0090 Proced
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Hash processor (HASH) RM0090 Bit 12
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Hash processor (HASH) RM0090 22.4.2
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Hash processor (HASH) RM0090 Bit 3
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Debug support (DBG) RM0090 33 Debug
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Debug support (DBG) RM0090 Figure 4
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Debug support (DBG) RM0090 33.4.3 I
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Debug support (DBG) RM0090 Only the
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Debug support (DBG) RM0090 Note: No
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Debug support (DBG) RM0090 31 30 29
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Debug support (DBG) RM0090 Bit 20:1
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Device electronic signature RM0090
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A ADC_CCR . . . . . . . . . . . . .
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DMA_SxM1AR . . . . . . . . . . . .
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HASH_SR . . . . . . . . . . . . . .
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RNG_DR . . . . . . . . . . . . . .
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Revision history RM0090 Revision hi
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Revision history RM0090 Table 238.
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