RM0090: Reference manual - STMicroelectronics

Ethernet (ETH): media access control (MAC) with DMA controller RM0090
Figure 326. Reduced media-independent interface signals
RMII clock sources
Either clock the PHY from an external 50 MHz clock or use a PHY with an embedded PLL to
generate the 50 MHz frequency.
Figure 327. RMII clock sources
25 MHz
29.4.4 MII/RMII selection
STM32 TXD[1:0]
TX_EN
STM32
The mode, MII or RMII, is selected using the configuration bit 23, MII_RMII_SEL, in the
SYSCFG_PMC register. The application has to set the MII/RMII mode while the Ethernet
controller is under reset or before enabling the clocks.
MII/RMII internal clock scheme
RXD[1:0]
CRS_DV
MDC
MDIO
REF_CLK
Clock source
The clock scheme required to support both the MII and RMII, as well as 10 and 100 Mbit/s
operations is described in Figure 328.
909/1416 Doc ID 018909 Rev 3
PLL
802.3 MAC
802.3 MAC
REF_CLK
50 MHz
External
PHY
External
PHY
For 10/100 Mbit/s
ai15624
MS19930V1