RM0090: Reference manual - STMicroelectronics

RM0090 USB on-the-go full-speed (OTG_FS)
Figure 364. Interrupt hierarchy
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17:10 9 8 7:3 2 1 0
Core interrupt
register (1)
Interrupt
sources
Device all endpoints
interrupt register
16:9
OUT endpoints
Device IN/OUT endpoint
interrupt registers 0 to 3
Host port control and status
register
Host all channels interrupt
register
Host channels interrupt
registers 0 to 7
3:0
IN endpoints
1. The core interrupt register bits are shown in OTG_FS core interrupt register (OTG_FS_GINTSTS) on
page 1055.
30.16 OTG_FS control and status registers
OTG
interrupt
register
Global interrupt
mask (Bit 0)
AHB configuration
register
AND
By reading from and writing to the control and status registers (CSRs) through the AHB
slave interface, the application controls the OTG_FS controller. These registers are 32 bits
wide, and the addresses are 32-bit block aligned. The OTG_FS registers must be accessed
by words (32 bits).
Doc ID 018909 Rev 3 1040/1416
OR
Core interrupt mask
register
Device all endpoints
interrupt mask register
Device IN/OUT
endpoints common
interrupt mask register
Host all channels
interrupt mask register
Host channels interrupt
mask registers 0 to 7
Interrupt
ai15616b