RM0090: Reference manual - STMicroelectronics

RM0090 USB on-the-go high-speed (OTG_HS)
receive FIFO accordingly. Following this, unmask the RXFLVL interrupt.
f) The core generates the RXFLVL interrupt for the transfer completion status entry
in the receive FIFO.
g) The application must read and ignore the receive packet status when the receive
packet status is not an IN data packet (PKTSTS in GRXSTSR ≠ 0b0010).
h) The core generates the XFRC interrupt as soon as the receive packet status is
read.
i) In response to the XFRC interrupt, disable the channel and stop writing the
OTG_HS_HCCHAR2 register for further requests. The core writes a channel
disable request to the nonperiodic request queue as soon as the
OTG_HS_HCCHAR2 register is written.
j) The core generates the RXFLVL interrupt as soon as the halt status is written to
the receive FIFO.
k) Read and ignore the receive packet status.
l) The core generates a CHH interrupt as soon as the halt status is popped from the
receive FIFO.
m) In response to the CHH interrupt, de-allocate the channel for other transfers.
n) Handling nonACK responses
● Control transactions in slave mode
Setup, Data, and Status stages of a control transfer must be performed as three
separate transfers. Setup-, Data- or Status-stage OUT transactions are performed
similarly to the bulk OUT transactions explained previously. Data- or Status-stage IN
transactions are performed similarly to the bulk IN transactions explained previously.
For all three stages, the application is expected to set the EPTYP field in
OTG_HS_HCCHAR1 to Control. During the Setup stage, the application is expected to
set the PID field in OTG_HS_HCTSIZ1 to SETUP.
● Interrupt OUT transactions
A typical interrupt OUT operation in Slave mode is shown in Figure 390. The
assumptions are:
– The application is attempting to send one packet in every frame (up to 1 maximum
packet size), starting with the odd frame (transfer size = 1 024 bytes)
– The periodic transmit FIFO can hold one packet (1 KB)
– Periodic request queue depth = 4
The sequence of operations is as follows:
a) Initialize and enable channel 1. The application must set the ODDFRM bit in
OTG_HS_HCCHAR1.
b) Write the first packet for channel 1. For a high-bandwidth interrupt transfer, the
application must write the subsequent packets up to MCNT (maximum number of
packets to be transmitted in the next frame times) before switching to another
channel.
c) Along with the last DWORD write of each packet, the OTG_HS host writes an
entry to the periodic request queue.
d) The OTG_HS host attempts to send an OUT token in the next (odd) frame.
e) The OTG_HS host generates an XFRC interrupt as soon as the last packet is
transmitted successfully.
f) In response to the XFRC interrupt, reinitialize the channel for the next transfer.
Doc ID 018909 Rev 3 1270/1416