RM0090: Reference manual - STMicroelectronics

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<strong>RM0090</strong> Secure digital input/output interface (SDIO) 28.9.7 SDIO data timer register (SDIO_DTIMER) Address offset: 0x24 Reset value: 0x0000 0000 The SDIO_DTIMER register contains the data timeout period, in card bus clock periods. A counter loads the value from the SDIO_DTIMER register, and starts decrementing when the data path state machine (DPSM) enters the Wait_R or Busy state. If the timer reaches 0 while the DPSM is in either of these states, the timeout status flag is set. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DATATIME rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw Bits 31:0 DATATIME: Data timeout period Data timeout period expressed in card bus clock periods. Note: A data transfer must be written to the data timer register and the data length register before being written to the data control register. 28.9.8 SDIO data length register (SDIO_DLEN) Address offset: 0x28 Reset value: 0x0000 0000 The SDIO_DLEN register contains the number of data bytes to be transferred. The value is loaded into the data counter when data transfer starts. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved DATALENGTH rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw Bits 31:25 Reserved, must be kept at reset value Bits 24:0 DATALENGTH: Data length value Number of data bytes to be transferred. Note: For a block data transfer, the value in the data length register must be a multiple of the block size (see SDIO_DCTRL). A data transfer must be written to the data timer register and the data length register before being written to the data control register. For an SDIO multibyte transfer the value in the data length register must be between 1 and 512. Doc ID 018909 Rev 3 888/1416
Secure digital input/output interface (SDIO) <strong>RM0090</strong> 28.9.9 SDIO data control register (SDIO_DCTRL) Address offset: 0x2C Reset value: 0x0000 0000 The SDIO_DCTRL register control the data path state machine (DPSM). 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved Bits 31:12 Reserved, must be kept at reset value 889/1416 Doc ID 018909 Rev 3 SDIOEN RWMOD RWSTOP RWSTART DBLOCKSIZE DMAEN DTMODE DTDIR DTEN rw rw rw rw rw rw rw rw rw rw rw rw Bit 11 SDIOEN: SD I/O enable functions If this bit is set, the DPSM performs an SD I/O-card-specific operation. Bit 10 RWMOD: Read wait mode 0: Read Wait control stopping SDIO_D2 1: Read Wait control using SDIO_CK Bit 9 RWSTOP: Read wait stop 0: Read wait in progress if RWSTART bit is set 1: Enable for read wait stop if RWSTART bit is set Bit 8 RWSTART: Read wait start If this bit is set, read wait operation starts. Bits 7:4 DBLOCKSIZE: Data block size Define the data block length when the block data transfer mode is selected: 0000: (0 decimal) lock length = 2 0 = 1 byte 0001: (1 decimal) lock length = 2 1 = 2 bytes 0010: (2 decimal) lock length = 2 2 = 4 bytes 0011: (3 decimal) lock length = 2 3 = 8 bytes 0100: (4 decimal) lock length = 2 4 = 16 bytes 0101: (5 decimal) lock length = 2 5 = 32 bytes 0110: (6 decimal) lock length = 2 6 = 64 bytes 0111: (7 decimal) lock length = 2 7 = 128 bytes 1000: (8 decimal) lock length = 2 8 = 256 bytes 1001: (9 decimal) lock length = 2 9 = 512 bytes 1010: (10 decimal) lock length = 2 10 = 1024 bytes 1011: (11 decimal) lock length = 2 11 = 2048 bytes 1100: (12 decimal) lock length = 2 12 = 4096 bytes 1101: (13 decimal) lock length = 2 13 = 8192 bytes 1110: (14 decimal) lock length = 2 14 = 16384 bytes 1111: (15 decimal) reserved Bit 3 DMAEN: DMA enable bit 0: DMA disabled. 1: DMA enabled.
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RM0090 Reference manual STM32F40x,
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Contents RM0090 3.5.3 Erase . . . .
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Contents RM0090 6.3.1 RCC clock con
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Contents RM0090 7.4.7 GPIO port bit
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Contents RM0090 10.3.4 Falling trig
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Contents RM0090 12.4.2 Independent
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Contents RM0090 14.3.3 Repetition c
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Contents RM0090 15.4.12 TIMx auto-r
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Contents RM0090 17.4.6 TIM6&TIM7 co
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Contents RM0090 22.1 HASH introduct
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Contents RM0090 24.3.3 Tx mailboxes
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Contents RM0090 26.3.14 Hardware fl
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Contents RM0090 28.4.13 SD I/O mode
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Contents RM0090 29.7 Ethernet inter
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Contents RM0090 31.3.1 High-speed O
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Contents RM0090 33.2 Reference ARM
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List of tables RM0090 List of table
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List of tables RM0090 Table 98. Tra
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List of tables RM0090 Table 192. NO
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List of figures RM0090 Figure 49. A
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List of figures RM0090 Figure 151.
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Documentation conventions RM0090 1
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Memory and bus architecture RM0090
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Embedded Flash memory interface RM0
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CRC calculation unit RM0090 4 CRC c
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CRC calculation unit RM0090 Bits 7:
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Power control (PWR) RM0090 Figure 7
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Power control (PWR) RM0090 When the
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Power control (PWR) RM0090 mode (se
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Power control (PWR) RM0090 A PVDO f
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Power control (PWR) RM0090 5.3.3 Sl
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Power control (PWR) RM0090 If an ac
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Power control (PWR) RM0090 I/O stat
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Power control (PWR) RM0090 Safe RTC
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Power control (PWR) RM0090 Bit 4 PV
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Power control (PWR) RM0090 5.4.3 PW
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Reset and clock control for (RCC) R
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DMA controller (DMA) RM0090 9 DMA c
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DMA controller (DMA) RM0090 9.3 DMA
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DMA controller (DMA) RM0090 Figure
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DMA controller (DMA) RM0090 Table 3
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DMA controller (DMA) RM0090 In dire
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DMA controller (DMA) RM0090 Figure
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DMA controller (DMA) RM0090 memory
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DMA controller (DMA) RM0090 9.3.11
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DMA controller (DMA) RM0090 9.4 DMA
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DMA controller (DMA) RM0090 Bits 25
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DMA controller (DMA) RM0090 9.5.5 D
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DMA controller (DMA) RM0090 Bits 8
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DMA controller (DMA) RM0090 15 14 1
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Interrupts and events RM0090 10 Int
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Interrupts and events RM0090 Table
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Interrupts and events RM0090 genera
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Interrupts and events RM0090 10.3 E
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Interrupts and events RM0090 15 14
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Basic timers (TIM6&TIM7) RM0090 17
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Basic timers (TIM6&TIM7) RM0090 Fig
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Basic timers (TIM6&TIM7) RM0090 17.
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Independent watchdog (IWDG) RM0090
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Independent watchdog (IWDG) RM0090
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Window watchdog (WWDG) RM0090 19 Wi
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Window watchdog (WWDG) RM0090 case,
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Window watchdog (WWDG) RM0090 19.6
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Window watchdog (WWDG) RM0090 19.6.
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Cryptographic processor (CRYP) RM00
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Random number generator (RNG) RM009
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Hash processor (HASH) RM0090 22.3 H
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Hash processor (HASH) RM0090 has le
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Hash processor (HASH) RM0090 The le
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Hash processor (HASH) RM0090 with v
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Hash processor (HASH) RM0090 Proced
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Hash processor (HASH) RM0090 Bit 12
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Hash processor (HASH) RM0090 22.4.2
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Hash processor (HASH) RM0090 Bit 3
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Hash processor (HASH) RM0090 HASH_H
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Hash processor (HASH) RM0090 Table
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Real-time clock (RTC) RM0090 23.2 R
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Real-time clock (RTC) RM0090 23.3.5
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Real-time clock (RTC) RM0090 RTC_TR
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Real-time clock (RTC) RM0090 window
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Real-time clock (RTC) RM0090 Bit 3
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Flexible static memory controller (
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Debug support (DBG) RM0090 33 Debug
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Debug support (DBG) RM0090 Figure 4
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Debug support (DBG) RM0090 33.4.3 I
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Debug support (DBG) RM0090 Only the
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Debug support (DBG) RM0090 Note: No
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Debug support (DBG) RM0090 33.9 AHB
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Debug support (DBG) RM0090 31 30 29
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Debug support (DBG) RM0090 Bit 20:1
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Device electronic signature RM0090
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A ADC_CCR . . . . . . . . . . . . .
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DMA_SxM1AR . . . . . . . . . . . .
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HASH_SR . . . . . . . . . . . . . .
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RNG_DR . . . . . . . . . . . . . .
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Revision history RM0090 Revision hi
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Revision history RM0090 Table 238.
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